Datasheet
MAX1997/MAX1998
Quintuple/Triple-Output TFT LCD Power Supplies
with Fault Protection and VCOM Buffer
______________________________________________________________________________________ 27
Stability Requirements
The MAX1997/MAX1998 linear-regulator controllers use
an internal transconductance amplifier to drive an
external pass transistor. The transconductance amplifi-
er, the pass transistor, the base-emitter resistor, and
the output capacitor determine the loop stability.
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base cur-
rent. The total DC loop gain is approximately:
where V
T
is 26mV at room temperature, h
FE
is the pass
transistor’s DC current gain, and I
BIAS
is the current
through the base-to-emitter resistor (R
BE
). Each of the
four linear-regulator controllers is designed for a differ-
ent maximum output current so they have different out-
put drive currents and different bias currents (I
BIAS
).
Each controller’s bias current can be found in the
Electrical Characteristics. The current listed in the
Conditions column for the FB_ Regulation Voltage
specification is the individual controller’s bias current.
The base-to-emitter resistor for each controller should
be chosen to set the correct I
BIAS
:
The output capacitor and the load resistance create the
dominant pole in the system. However, the internal
amplifier delay, the pass transistor’s input capacitance,
and the stray capacitance at the feedback node create
additional poles in the system, and the output capacitor’s
ESR generates a zero. For proper operation, use the
following steps to ensure the linear regulator stability:
1) First, calculate the dominant pole set by the linear
regulator’s output capacitor and the load resistor:
where C
LDO
is the output capacitance of the LDO
and R
LOAD
is the load resistance corresponding to
the maximum load current.
The unity gain crossover of the linear regulator is:
f
CROSSOVER
= A
V(LDO)
f
POLE(LDO)
2) The pole caused by the internal amplifier delay is at
about 1MHz:
f
POLE(AMP)
≅ 1MHz
3) Next, calculate the pole set by the transistor’s input
capacitance, the transistor’s input resistance, and
the base-to-emitter pullup resistor:
Because R
BE
is much greater than R
IN
, the above
equation can be simplified:
where g
m
is the transconductance of the pass tran-
sistor, and f
T
is the transition frequency. Both para-
meters can be found in the transistor’s data sheet.
Therefore, the equation can be further simplified:
4) Next, calculate the pole set by the linear regulator’s
feedback resistance and the capacitance between
FB_ and GND (approximately 5pF including stray
capacitance):
and
5) Next, calculate the zero caused by the output
capacitor’s ESR:
where R
ESR
is the equivalent series resistance of
C
LDO
.
f
CR
ESR ZERO
LDO ESR
_
=
1
2π
f
CR R
POLE FB N
FB
()_
(||)
=
1
21617π
f
CR R
f
CR R
f
CR R
POLE FB P
FB
POLE FB
FB
POLE FB
FB
()_
()_
()_
(||)
(||)
(|| )
=
=
=
1
21920
1
28899
1
21112
1
2
π
π
π
f
f
POLE(CIN)
T
=
h
FE
f
1
C
g
h
g
POLE(CIN)
II
m
I
FE
m
≈
=
==
2
2
π
π
π
CR
f
RR
NN
IN
T
N
f
1
I)
POLE(CIN)
BE IN
=
2πCNR R
II
(
f
1
POLE(LDO)
LDO LOAD
=
2πCR
R
V
BE
BE
BIAS
=
I
A
4
V
h
I
V
V(LDO)
T
BIAS FE
LOAD
REF
=
+
1
I