Datasheet

MAX1997/MAX1998
Quintuple/Triple-Output TFT LCD Power Supplies
with Fault Protection and VCOM Buffer
12 ______________________________________________________________________________________
PIN
MAX1997
MAX1998
NAME FUNCTION
19 — DRV2
Gamma Linear-Regulator (REG 2) Base Drive. Open drain of an internal N-channel MOSFET.
Connect DRV2 to the base of an external PNP linear regulator pass transistor. (See the Pass
Transistor Selection section.)
20 11 FB
Main Step-Up Regulator Feedback Input. Connect FB to the center tap of a resistive voltage-
divider between the main output (V
MAIN
) and the analog ground (GND) to set the main step-
up regulator output voltage. (See the Main Step-Up Regulator, Output Voltage Selection
section.) Place the resistive voltage-divider close to the pin.
21 12 FBP
G ate- On Li near - Reg ul ator ( RE G P ) Feed b ack Inp ut. FBP r eg ul ates to 1.25V nom i nal . C onnect
FBP to the center tap of a r esi sti ve vol tag e- d i vi d er b etw een the RE G P outp ut and the anal og
g r ound ( GN D ) to set the outp ut vol tag e. P l ace the r esi sti ve vol tag e- d i vi d er cl ose to the p i n.
22 13 DRVP
Gate-On Linear-Regulator (REG P) Base Drive. Open drain of an internal N-channel MOSFET.
Connect DRVP to the base of an external PNP linear-regulator pass transistor. (See the Pass
Transistor Selection section.)
23 14 LX
Switching Node. Drain of the internal N-channel power MOSFET for the main step-up
regulator.
24 15
TGNDA
Internal Connection. Connect this pin to ground. Do not leave this pin floating.
25 16 OCN
Overcurrent Comparator Inverting Input. Connect OCN to the center tap of a resistive
voltage-divider connected to the drain of the external input protection P-channel MOSFET.
(See the Input Overcurrent Protection section.) If unused, connect OCN to REF.
26 17 OCP
Overcurrent Comparator Noninverting Input. Connect OCP to the center tap of a resistive
voltage-divider connected to the source of the external input protection P-channel MOSFET.
The voltage on OCP sets the input overcurrent threshold. (See the Input Overcurrent
Protection section.) If unused, connect OCP to GND.
27 18 GATE
Gate-Drive Output to the External Input Protection P-Channel MOSFET. (See the Input
Overcurrent Protection section.) If unused, leave GATE unconnected.
28 — PFLT
Fault Timer Select Input. Pull PFLT above its logic high threshold (0.7 × V
IN
) to set the fault
delay period to 87ms. Pull PFLT below its logic low threshold (0.3 × V
IN
) to set the fault delay
period to 22ms. Leave PFLT unconnected to set the fault delay period to 44ms. The fault
delay period for the MAX1998 is fixed at 87ms.
29 19 IN
Supply Input. The supply voltage powers all the control circuitry. The input voltage range is
from 2.7V to 5.5V. Bypass IN to GND with a 0.47µF ceramic capacitor. Place the capacitor
within 5mm of IN.
30 — ONDC
S tep - U p Reg ul ator Log i c C ontr ol Inp ut. The step - up r eg ul ator , V C O M b uffer , and the seq uence
ti m i ng b l ock ar e enab l ed w hen O N D C i s hi g h and d i sab l ed w hen ON D C i s l ow .
31 20 FREQ
Frequency Select Input. Pull FREQ above its logic high threshold (0.7 × V
IN
) to set the main
step-up regulator switching frequency to 1.5MHz. Pull FREQ below its logic low threshold
(0.3 × V
IN
) to set the frequency to 375kHz. Leave FREQ unconnected to set the frequency
to 750kHz.
32 — SHDN
Active-Low Shutdown Control Input. All the sections of the device are disabled and the GATE
pin goes high when SHDN is below its 0.4V logic low threshold. Pull SHDN above its 1.6V
logic high threshold to enable the device. Do not leave SHDN unconnected.
Pin Description (continued)