Datasheet

Note 3: Includes power FET leakage.
Note 4: CTLI gain is defined as:
Note 5: Specifications to -40°C are guaranteed by design, not production tested.
A
CTLI
VV
VV
CTLI REF
OSI CS
=
−
()
−
()
Integrated Temperature
Controllers for Peltier Modules
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= PV
DD
1 = PV
DD
2 = V
SHDN
= 5V, FREQ = GND, CTLI = FB+ = FB- = MAXV = MAXIP = MAXIN = REF, T
A
= -40°C to +85°C,
unless otherwise noted.) (Note 5)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
V
MAXV
= V
REF
✕
0.67,
V
OS1
to V
OS2
= ±4V, V
DD
= 5V
-1 +1
MAXV Threshold Accuracy
V
MAXV
= V
REF
✕
0.33, V
OS1
to V
OS2
= ±2V,
V
DD
= 3V
-2 +2
%
MAXV, MAXIP, MAXIN
Input Bias Current
I
MAXV-BIAS
,
I
MAXI_-BIAS
V
MAXV
= V
MAXI_
= 0.1V or 1.5V -0.1 +0.1 µA
CTLI Gain A
CTLI
V
CTLI
= 0.5V to 2.5V (Note 4) 9.5 10.5 V/V
CTLI Input Resistance R
CTLI
1MΩ terminated at REF 0.5 2.0 MΩ
Error Amp Transconductance g
m
50 175 µS
ITEC Accuracy V
OS1
to V
CS
= +100mV or -100mV -10 +10 %
ITEC Load Regulation ∆V
ITEC
V
OS1
to V
CS
= +100mV or
-100mV, I
ITEC
= ±10µA
-0.125 +0.125 %
Instrumentation Amp
Input Bias Current
I
DIF-BIAS
-10 +10 nA
Instrumentation Amp
Offset Voltage
V
DIF-OS
V
DD
= 3V to 5.5V -200 +200 µV
Instrumentation Amp
Preset Gain
A
DIF
R
LOAD
= 10kΩ to REF 45 55 V/V
Integrator Amp Input Bias Current I
INT-BIAS
V
DD
= 3V to 5.5V 1 nA
Integrator Amp Voltage Offset V
INT-OS
V
DD
= 3V to 5.5V -3 +3 mV
Undedicated Chopper Amp Input
Bias Current
I
AIN-BIAS
V
DD
= 3V to 5.5V -10 +10 nA
Undedicated Chopper Amp
Offset Voltage
V
AIN-OS
V
DD
= 3V to 5.5V -200 +200 µV
BFB_ Buffer Error C
LOAD
< 100pF -200 +200 µV
UT and OT Leakage Current I
LEAK
V
UT
= V
OT
= 5.5V 1 µA
UT and OT Output Low Voltage V
OL
Sinking 4mA 150 mV
MAX1978/MAX1979
6
Maxim Integrated