Datasheet

MAX19706
10-Bit, 22Msps, Ultra-Low-Power
Analog Front-End
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ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈ 10pF on all digital outputs, f
CLK
= 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
REFP
= C
REFN
=
C
COM
= 0.33µF, unless otherwise noted. C
L
< 5pF on all aux-DAC outputs. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Standby mode: CLK = 0 or OV
DD
;
aux-DACs ON and at midscale,
aux-ADC ON
35
Idle mode: f
CLK
= 22MHz; aux-DACs ON
and at midscale, aux-ADC ON
812
mA
V
DD
Supply Current
Shutdown mode: CLK = 0 or OV
DD
0.8 µA
Ext1-Rx, Ext2-Rx, Ext3-Rx, Ext4-Rx,
SPI1-Rx, SPI3-Rx states; receive ADC
operating mode (Rx): f
CLK
= 22MHz,
f
IN
= 5.5MHz on both channels;
aux-DACs ON and at midscale,
aux-ADC ON
4.8 mA
Ext1-Tx, Ext2-Tx, Ext3-Tx, Ext4-Tx,
SPI2-Tx, SPI4-Tx states; transmit DAC
operating mode (Tx): f
CLK
= 22MHz, f
OUT
= 2.2MHz on both channels; aux-DACs
ON and at midscale, aux-ADC ON
247
Standby mode: CLK = 0 or OV
DD
; aux-
DACs ON and at midscale, aux-ADC ON
0.7
Idle mode: f
CLK
= 22MHz; aux-DACs ON
and at midscale, aux-ADC ON
37.8
OV
DD
Supply Current
Shutdown mode: CLK = 0 or OV
DD
0.7
µA
Rx ADC DC ACCURACY
Resolution N 10 Bits
Integral Nonlinearity INL ±0.9 LSB
Differential Nonlinearity DNL ±0.45 LSB
Offset Error Residual DC offset error -5 ±1 +5 %FS
Gain Error Include reference error -5 ±0.85 +5 %FS
DC Gain Matching -0.15 ±0.001 +0.15 dB
Offset Matching ±7.4 LSB
Gain Temperature Coefficient ±17 ppm/°C
Offset error (V
DD
±5%) ±2 LSB
Power-Supply Rejection PSRR
Gain error (V
DD
±5%) ±0.06 %FS