Datasheet

MAX19706
10-Bit, 22Msps, Ultra-Low-Power
Analog Front-End
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bus contention in these states, the Rx ADC output
buffers are tri-stated during Tx and the Tx DAC input
bus is tri-stated during Rx.
In SLOW mode, the Rx ADC core is off during Tx; likewise
the Tx DAC is turned off during Rx to yield lower power
consumption in these modes. For example, the power in
SLOW Tx mode is 33.9mW. The power consumption dur-
ing Rx is 39.3mW compared to 46.8mW power consump-
tion in FAST mode. However, the recovery time between
states is increased. The switching time in SLOW mode
between Rx to Tx is 6µs and Tx to Rx is 8.1µs.
External T/
RR
Switching Control vs.
Serial-Interface Control
Bit E3 in the ENABLE-16 or ENABLE-8 register deter-
mines whether the device Tx-Rx mode is controlled
externally through the T/R input (E3 = low) or through the
SPI command (E3 = high). By default, the MAX19706 is
in the external Tx-Rx control mode. In the external control
mode, use the T/R input (pin 27) to switch between Rx
and Tx modes. Using the T/R pin provides faster switch-
ing between Rx and Tx modes. To override the external
Tx-Rx control, program the MAX19706 through the serial
interface. During SHDN, IDLE, or STBY modes, the T/R
input is overridden. To restore external Tx-Rx control,
program bit E3 low and exit the SHDN, IDLE, or STBY
modes through the serial interface.
When using SPI commands exclusively to control Tx-Rx
states (external T/R pin is not used), then the T/R pin
must be pulled up to OV
DD
or pulled down to OGND.
SPI Timing
The serial digital interface is a standard 3-wire connec-
tion compatible with SPI/QSPI™/MICROWIRE/DSP inter-
faces. Set CS low to enable the serial data loading at
DIN or output at DOUT. Following a CS high-to-low tran-
sition, data is shifted synchronously, most significant bit
first, on the rising edge of the serial clock (SCLK). After
16 bits are loaded into the serial input register, data is
transferred to the latch when CS transitions high. CS
must transition high for a minimum of 80ns before the
next write sequence. The SCLK can idle either high or
low between transitions. Figure 6 shows the detailed
timing diagram of the 3-wire serial interface.
QSPI is a trademark of Motorola, Inc.
Figure 6. Serial-Interface Timing Diagram
16-BIT OR 8-BIT WRITE INTO SPI (DIN) 16-BIT OR 8-BIT WRITE
INTO SPI DURING
AUX-ADC CONVERSION
10-BIT READ OUT OF AUX-ADC (DOUT) WITH
SIMULTANEOUS 16-BIT WRITE INTO SPI (DIN)
t
CHZ
LSB
BIT A0
(DIN)
BIT D1
(DIN)
LSBMSB
BIT D10
(DIN)
LSB
A0
DOUT = TRI-STATED WHEN
AUX-ADC IS IDLE
DOUT = ACTIVE WHEN
BIT AD0 IS SET
AUX-ADC
IS BUSY
AUX-ADC
DATA READY
MSB
BIT D9
(DOUT)
LSB
BIT D0
(DOUT)
LSB
BIT D0
(HELD)
DOUT
TRI-
STATED
BIT AD0
CLEARED
D10 (16-BIT)
D2 (8-BIT)
MSB
D11 (16-BIT)
D3 (8-BIT)
MSB
BIT D11
(DIN)
t
DCS
t
CONV
t
CSD
t
CS
t
CP
t
CSS
t
CSW
t
DS
t
CH
t
CL
t
DH
t
CD
SCLK
CS
DIN
DOUT