Datasheet
MAX19706
10-Bit, 22Msps, Ultra-Low-Power
Analog Front-End
18 ______________________________________________________________________________________
Figure 3. Rx ADC System Timing Diagram
t
DOQ
t
CL
t
CH
t
CLK
t
DOI
5 CLOCK-CYCLE LATENCY (CHI)
5.5 CLOCK-CYCLE LATENCY (CHQ)
D0–D9
D0Q D1I D1Q D2I D2Q D3I D3Q D4I D4Q D5I D5Q D6I D6Q
CHI
CHQ
CLK
Table 2. Tx DAC Output Voltage vs. Input Codes
(Internal Reference Mode V
REFDAC
= 1.024V, External Reference Mode V
REFDAC
= V
REFIN
; V
FS
= 400 for 800mV
P-P
Full Scale)
DIFFERENTIAL OUTPUT VOLTAGE
(
V
)
OFFSET BINARY (D0–D9) INPUT DECIMAL CODE
11 1111 1111 1023
11 1111 1110 1022
10 0000 0001 513
10 0000 0000 512
01 1111 1111 511
00 0000 0001 1
00 0000 0000 0
V
V
FS
REFDAC
1024
1023
1023
()
×
V
V
FS
REFDAC
1024
1021
1023
()
×
V
V
FS
REFDAC
1024
3
1023
()
×
V
V
FS
REFDAC
1024
1
1023
()
×
V
V
FS
REFDAC
1024
1
1023
()
×
−
V
V
FS
REFDAC
1024
1021
1023
()
×
−
V
V
FS
REFDAC
1024
1023
1023
()
×
−
Dual, 10-Bit Tx DAC
The dual, 10-bit digital-to-analog converter (Tx DAC)
operates with clock speeds up to 22MHz. The Tx DAC
digital inputs, D0–D9, are multiplexed on a single 10-bit
bus. The voltage reference determines the Tx DAC full-
scale output voltage. See the Reference Configurations
section for details on setting the reference voltage.
The Tx DAC outputs at IDN, IDP and QDN, QDP are
biased at a 0.9V to 1.35V adjustable DC common-
mode bias and designed to drive a differential input
stage with ≥ 70kΩ input impedance. This simplifies the
analog interface between RF quadrature upconverters
and the MAX19706. Many RF upconverters require a
0.9V to 1.35V common-mode bias. The Tx DAC DC
common-mode bias eliminates discrete level-setting
resistors and code-generated level shifting while pre-
serving the full dynamic range of each Tx DAC. The Tx
DAC differential analog outputs cannot be used in sin-
gle-ended mode because of the internally generated
common-mode DC level. Table 2 shows the Tx DAC
output voltage vs. input codes. Table 10 shows the
selection of DC common-mode levels. See Figure 4 for
an illustration of the Tx DAC analog output levels.