Datasheet

MAX19706
10-Bit, 22Msps, Ultra-Low-Power
Analog Front-End
______________________________________________________________________________________ 17
Rx ADC System Timing Requirements
Figure 3 shows the relationship between the clock, ana-
log inputs, and the resulting output data. Channel I
(CHI) and channel Q (CHQ) are sampled on the rising
edge of the clock signal (CLK) and the resulting data is
multiplexed at the D0–D9 outputs. CHI data is updated
on the rising edge and CHQ data is updated on the
falling edge of the CLK. Including the delay through the
output latch, the total clock-cycle latency is 5 clock
cycles for CHI and 5.5 clock cycles for CHQ.
Digital Input/Output Data (D0–D9)
D0–D9 are the Rx ADC digital logic outputs when the
MAX19706 is in receive mode. This bus is shared with
the Tx DAC digital logic inputs and operates in half-
duplex mode. D0–D9 are the Tx DAC digital logic inputs
when the MAX19706 is in transmit mode. The logic level
is set by OV
DD
from 1.8V to V
DD
. The digital output cod-
ing is offset binary (Table 1). Keep the capacitive load
on the digital outputs D0–D9 as low as possible (< 15pF)
to avoid large digital currents feeding back into the ana-
log portion of the MAX19706 and degrading its dynamic
performance. Buffers on the digital outputs isolate the
outputs from heavy capacitive loads. Adding 100Ω resis-
tors in series with the digital outputs close to the
MAX19706 will help improve Rx ADC and Tx DAC per-
formance. Refer to the MAX19707EVKIT schematic for
an example of the digital outputs driving a digital buffer
through 100Ω series resistors.
During SHDN, IDLE, and STBY states, D0–D9 are inter-
nally pulled up to prevent floating digital inputs. To
ensure no current flows through D0–D9 I/O, the external
bus needs to be either tri-stated or pulled up to OV
DD
.
Do not pull the external bus to ground.
Table 1. Rx ADC Output Codes vs. Input Voltage
DIFFERENTIAL INPUT
VOLTAGE
DIFFERENTIAL INPUT
(
LSB
)
OFFSET BINARY (D0–D9) OUTPUT DECIMAL CODE
V
REF
x 512/512 511 (+Full Scale - 1 LSB) 11 1111 1111 1023
V
REF
x 511/512 510 (+Full Scale - 2 LSB) 11 1111 1110 1022
V
REF
x 1/512 [phone]
V
REF
x 0/512 0 (Bipolar Zero) 10 0000 0000 512
-V
REF
x 1/512 -1 01 1111 1111 511
-V
REF
x 511/512 -511 (-Full Scale +1 LSB) 00 0000 0001 1
-V
REF
x 512/512 -512 (-Full Scale) 00 0000 0000 0
Figure 2. Rx ADC Transfer Function
INPUT VOLTAGE (LSB)
-1
-510 -509
1024
2 x V
REF
1 LSB =
V
REF
= V
REFP
- V
REFN
V
REF
V
REF
V
REF
V
REF
0+
1
-511
+510
+512
+511-512 +509
(COM)
(COM)
OFFSET BINARY OUTPUT CODE (LSB)
00 0000 0000
00 0000 0001
00 0000 0010
00 0000 0011
11 1111 1111
11 1111 1110
11 1111 1101
01 1111 1111
10 0000 0000
10 0000 0001