Datasheet

MAX19706
10-Bit, 22Msps, Ultra-Low-Power
Analog Front-End
16 ______________________________________________________________________________________
Figure 1. Rx ADC Internal T/H Circuits
S3b
S3a
COM
S5b
S5a
QAP
QAN
S1
OUT
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
HOLD
HOLD
CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
TRACK
TRACK
S2a
S2b
S3b
S3a
COM
S5b
S5a
IAP
IAN
S1
OUT
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
S2a
S2b
MAX19706
Dual, 10-Bit Rx ADC
The ADC uses a seven-stage, fully differential, pipelined
architecture that allows for high-speed conversion while
minimizing power consumption. Samples taken at the
inputs move progressively through the pipeline stages
every half clock cycle. Including the delay through the
output latch, the total clock-cycle latency is 5 clock
cycles for channel IA and 5.5 clock cycles for channel
QA. The ADC full-scale analog input range is ±V
REF
with a V
DD
/ 2 (±200mV) common-mode input range.
V
REF
is the difference between V
REFP
and V
REFN
. See
the Reference Configurations section for details.
Input Track-and-Hold (T/H) Circuits
Figure 1 displays a simplified diagram of the Rx ADC
input track-and-hold (T/H) circuitry. Both ADC inputs
(IAP, QAP, IAN, and QAN) can be driven either differen-
tially or single-ended. Match the impedance of IAP and
IAN, as well as QAP and QAN, and set the input signal
common-mode voltage within the V
DD
/ 2 (±200mV)
Rx ADC range for optimum performance.