Datasheet

MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
_______________________________________________________________________________________ 7
______________________________________________________________Pin Description
Digital GroundDGND28
+5V Supply. Bypass with 0.1µF capacitor to AGND.V
DD
27
In the internal acquisition mode, when CSis low, a rising edge on WR latches in configuration data and starts an
acquisition plus a conversion cycle. In the external acquisition mode, when CSis low, the first rising edge on WR
starts an acquisition, and a second rising edge on WRends acquisition and starts a conversion cycle.
WR26
PIN
Chip Select, active lowCS2
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock. In internal clock mode,
place a capacitor (C
CLK
) from this pin to ground to set the internal clock frequency; f
CLK
= 1.56MHz typical
with C
CLK
= 100pF.
CLK1
FUNCTIONNAME
100k
510k
24k
REFADJ
+5V
0.01µF
MAX196
MAX198
Figure 1. Reference-Adjust Circuit
3k
3k
D
OUT
D
OUT
+5V
a) High-Z to V
OH
and V
OL
to V
OH
b) High-Z to V
OL
and V
OH
to V
OL
C
LOAD
C
LOAD
Figure 2. Load Circuits for Enable Time
_______________Detailed Description
Converter Operation
The MAX196/MAX198 multirange, fault-tolerant ADCs
use successive approximation and internal input
track/hold (T/H) circuitry to convert an analog signal to
a 12-bit digital output. The 12-bit parallel-output format
provides easy interface to microprocessors (µPs).
Figure 3 shows the MAX196/MAX198 in the simplest
operational configuration.
Analog-Input Track/Hold
In the internal acquisition control mode (control bit D5
set to 0), the T/H enters its tracking mode on WR’s ris-
ing edge, and enters its hold mode when the internally
timed (6 clock cycles) acquisition interval ends. In bipo-
lar mode and unipolar mode (MAX196 only), a low-
impedance input source, which settles in less than
1.5µs, is required to maintain conversion accuracy at
the maximum conversion rate.
When the MAX198 is configured for unipolar mode, the
input does not need to be driven from a low-impedance
source. The acquisition time (t
AZ
) is a function of the
source output resistance (R
S
), the channel input resis-
tance (R
IN
), and the T/H capacitance.
Three-State Digital I/O, D11 = MSBD11–D03–14
Analog GroundAGND15
Analog Input ChannelsCH0–CH516–21
Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01µF capacitor to AGND. Connect
to V
DD
when using an external reference at the REF pin.
REFADJ22
Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a
4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal
buffer by pulling REFADJ to V
DD
.
REF23
INT goes low when conversion is complete and output data is ready.INT24
If CS is low, a falling edge on RD will enable a read operation on the data bus.RD25