Datasheet

Compensation with Electrolytic Output Capacitors
The MAX1960/MAX1961/MAX1962 use a voltage-mode
control scheme that regulates the output voltage by
comparing the error-amplifier output (COMP) with a
fixed internal ramp to produce the required duty cycle.
The inductor and output capacitor create a double pole
at the resonant frequency, which has gain drop of 40dB
per decade, and phase shift of 180°. The error amplifier
must compensate for this gain drop and phase shift in
order to achieve a stable high-bandwidth, closed-loop
system.
The basic regulator loop consists of a power modulator,
an output feedback divider and an error amplifier. The
power modulator has DC gain set by V
IN
/V
RAMP
, with a
double pole set by the inductor and output capacitor,
and a single zero set by the output capacitor (C
O
) and
its equivalent series resistance (ESR). Below are equa-
tions that define the power modulator:
The DC gain of the power modulator is:
where V
RAMP
= 0.85 × 10
6
/ f
S
. The pole frequency due
to the inductor and output capacitor is:
The zero frequency due to the output capacitor’s ESR
is:
The output capacitor is usually comprised of several
same value capacitors connected in parallel. With n
capacitors in parallel, the output capacitance is:
The total ESR is:
The ESR zero (f
ZESR
) for a parallel combination of
capacitors is the same as for an individual capacitor.
The feedback divider has a gain of G
FB
= V
FB
/V
OUT
,
where V
FB
is 0.8V.
The transconductance error amplifier has DC gain
GEA(dc) of 80dB. A dominant pole is set by the com-
pensation capacitor (C
C
), the amplifier output resis-
tance (R
O
), and the compensation resistor (R
C
):
A zero is set by the compensation resistor and the
compensation capacitor:
The total closed-loop gain must equal to unity at the
crossover frequency, where the crossover frequency
should be higher than f
ZESR
, so that the -1 slope is
used to cross over at unity gain. Also, the crossover
frequency should be less than or equal to 1/5 the
switching frequency.
The loop-gain equation at the crossover frequency is:
where:
and:
The compensation resistor, R
C
, is calculated from:
where g
mEA
= 2mS.
Due to the under-damped (Q > 1) nature of the output
LC double pole, the error-amplifier compensation zero
should be approximately 0.2f
PMOD
to provide good
phase boost. C
C
is calculated from:
R
V
gVG
C
OUT
mEA FB MOD f
C
=
××
()
GG
f
ff
MOD f MOD DC
PMOD
ESR C
C
() ( )
()
=×
×
2
GgR
EA f mEA C
C
()
=×
V
V
GG
FB
OUT
EA f MOD f
CC
() ()
×× =1
ff
f
ZESR C
S
<≤
5
f
CR
ZEA
CC
=
××
1
2π
f
CRR
PEA
CC
=
××+
1
2
0
π ( )
R
R
n
ESR
ESR EACH
=
()
CnC
O EACH
=×
f
RC
ZESR
ESR O
=
××
1
2π
f
LC
PMOD
OO
=
1
2π
G
V
V
MOD DC
IN
RAMP
()
=
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
______________________________________________________________________________________ 17