Datasheet

MAX1954A
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
______________________________________________________________________________________ 13
choose the high-side MOSFET (N1) that has conduction
losses equal to switching loss at nominal input voltage
and output current. The selected MOSFETs must have an
R
DS(ON)
that satisfies the current-limit setting condition
above. For N2, ensure that it does not spuriously turn on
due to dV/dt caused by N1 turning on, as this would
result in shoot-through current degrading the efficiency.
MOSFETs with a lower Q
gd
/Q
gs
ratio have higher immuni-
ty to dV/dt.
For proper thermal-management design, the power dis-
sipation must be calculated at the desired maximum
operating junction temperature, T
J(MAX)
. N1 and N2
have different loss components due to the circuit oper-
ation. N2 operates as a zero-voltage switch; therefore,
major losses are the channel-conduction loss (P
N2CC
)
and the body-diode conduction loss (P
N2DC
).
where V
F
is the body-diode forward-voltage drop, t
dt
is
the dead time between N1 and N2 switching transitions,
f
S
is the switching frequency, and t
dt
is 20ns (typ).
N1 operates as a duty-cycle control switch and has the
following major losses: the channel-conduction loss
(P
N1CC
), the VL overlapping switching loss (P
N1SW
),
and the drive loss (P
N1DR
). N1 does not have body-
diode conduction loss, because the diode never con-
ducts current.
where I
GATE
is the average DH-driver output current
capability determined by:
where R
DS(ON)(N2)
is the high-side MOSFET driver’s
on-resistance (1.5Ω typ) and R
GATE
is the internal gate
resistance of the MOSFET (~2Ω).
where V
GS
~V
IN.
In addition to the losses above, allow approximately
20% for additional losses due to MOSFET output capac-
itances and N2 body-diode reverse-recovery charge
dissipated in N1 that exists, but is not well defined, in
the MOSFET data sheet. Refer to the MOSFET data
sheet for thermal-resistance specification to calculate
the PC board area needed to maintain the desired maxi-
mum operating junction temperature with the above cal-
culated power dissipations.
To reduce electromagnetic interference (EMI) caused
by switching noise, add a 0.1µF ceramic capacitor from
the high-side switch drain to the low-side switch source
or add resistors in series with DH and DL to slow down
the switching transitions. However, adding series resis-
tors increases the power dissipation of the MOSFET, so
be sure this does not overheat the MOSFET.
The minimum load current must exceed the high-side
MOSFET’s maximum leakage-current overtemperature
if fault conditions are expected.
MOSFET Snubber Circuit
Fast-switching transitions cause ringing because of
resonating circuit parasitic inductance and capaci-
tance at the switching nodes. This high-frequency ring-
ing occurs at LX’s rising and falling transitions and can
interfere with circuit performance and generate EMI. To
dampen this ringing, a series RC snubber circuit is
added across each switch. Below is the procedure for
selecting the value of the series RC circuit:
1) Connect a scope probe to measure the voltage
from LX to GND, and observe the ringing frequen-
cy, f
R
.
2) Find the capacitor value (connected from LX to
GND) that reduces the ringing frequency by half.
The circuit parasitic capacitance (C
PAR
) at LX is then
equal to 1/3rd of the value of the added capacitance
above. The circuit parasitic inductance (L
PAR
) is calculat-
ed by:
The resistor for critical dampening (R
SNUB
) is equal to
2π x f
R
x L
PAR
. Adjust the resistor value up or down to
tailor the desired damping and the peak voltage excur-
sion. The capacitor (C
SNUB
) should be at least two to
four times the value of the C
PAR
to be effective. The
power loss of the snubber circuit (P
RSNUB
) is dissipat-
ed in the resistor R
SNUB
and can be calculated as:
PCVf
RSNUB SNUB IN S
=×
()
×
2
L
fC
PAR
R PAR
=
()
×
1
2
2
π
PQVf
R
RR
NDR g GS
S
GATE
GATE DS ON N
1
2
=× ××
+
()()
I
V
RR
GATE
IN
DS ON N GATE
.
()()
≅×
+
05
2
.
()
() ( )
P
V
V
IR
Use R at T
PVI
QQ
I
f
NCC
OUT
IN
LOAD
DS ON
DS ON J MAX
N SW IN LOAD
gs gd
GATE
S
1
2
1
=
⎛
⎝
⎜
⎞
⎠
⎟
××
=× ×
+
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
×
(
.
() ( )
() ( )
VR I
LIR
I
Use R at T
PIVtf
VALLEY DS ON LOAD MAX LOAD MAX
DS ON J MAX
N DC LOAD F dt S
=× −
⎛
⎝
⎜
⎞
⎠
⎟
×
=× × × ×
()
2
2
2