Datasheet
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
12 ______________________________________________________________________________________
SSTRB
CS
SCLK
DIN
DOUT
1 4 8 12 16 20 24
START
SEL2 SEL1 SEL0
UNI/
BIP
SGL/
DIF
PD1 PD0
B9
MSB
B8 B7 B6 B5 B4 B3 B2 B1
B0
LSB
S1
SO
ACQUISITION
1.5µs (CLK = 2MHz)
IDLE
FILLED WITH
ZEROS
IDLE
CONVERSION
t
ACQ
A/D STATE
RB1
RB1 RB2 RB3
RB2
RB3
• • •
• • •
• • •
• • •
CS
SCLK
DIN
DOUT
t
CSH
t
CSS
t
CL
t
DS
t
DH
t
DV
t
CH
t
DO
t
TR
t
CSH
Figure 6. 24-Bit External Clock Mode Conversion Timing (SPI, QSPI and Microwire Compatible)
Figure 7. Detailed Serial-Interface Timing
Pulling CS high prevents data from being clocked into
the MAX192 and three-states DOUT, but it does not
adversely affect an internal clock-mode conversion
already in progress. When internal clock mode is
selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shifted in
and out of the MAX192 at clock rates exceeding
4.0MHz, provided that the minimum acquisition time,
t
AZ
, is kept above 1.5µs.
Data Framing
The falling edge of CS does not start a conversion on
the MAX192. The first logic high clocked into DIN is inter-
preted as a start bit and defines the first bit of the control
byte. A conversion starts on the falling edge of SCLK,
after the eighth bit of the control byte (the PD0 bit) is
clocked into DIN. The start bit is defined as:
The first high bit clocked into DIN with CS low any-
time the converter is idle, e.g. after V
DD
is applied.
OR
The first high bit clocked into DIN after bit 3 of a
conversion in progress is clocked onto the DOUT pin.
If a falling edge on CS forces a start bit before bit 3
(B3) becomes available, then the current conversion
will be terminated and a new one started. Thus, the
fastest the MAX192 can run is 15 clocks per conver-
sion. Figure 11a shows the serial-interface timing nec-
essary to perform a conversion every 15 SCLK cycles
in external clock mode. If CS is low and SCLK is contin-
uous, guarantee a start bit by first clocking in 16 zeros.