Datasheet

MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
_______________________________________________________________________________________ 7
Pin Description
Clock Input/Serial Clock Input in serial mode. An external TTL-/CMOS-compatible clock may be applied to
this pin, or a capacitor (120pF nominal) may be connected between CLK and DGND to operate the internal
oscillator.
High-Byte Enable Input. In parallel mode, HBEN = high multiplexes the 4 MSBs of the conversion result
into the lower bit outputs. HBEN = high also disables conversion starts. HBEN = low places the 8 LSBs
onto the data bus. In serial mode, HBEN = low enables SCLK
OUT
to operate during the conversion only,
HBEN = high enables SCLK
OUT
to operate continuously, provided CS is low.
Chip-Select Input must be low for the ADC to recognize RD and HBEN inputs in parallel mode. The falling
edge of CS starts a conversion in serial mode. CS = high in serial mode forces SCLK
OUT
, SSTRB, and
DOUT into a high-impedance state.
Read Input. In parallel mode, a low signal starts a conversion when CS and HBEN are low (memory
mode). RD also enables the outputs when CS is low. In serial mode, RD = low enables SCLK
OUT
and
SSTRB when CS is low. RD = high forces SCLK
OUT
and SSTRB into a high-impedance state.
D6/SCLK
OUT
7 Analog GroundAGND
24 Positive Supply, +5V ±5%V
DD
23 CLK/SCLK
22 Sets the output mode. PAR = high selects parallel output mode. PAR = low selects serial output mode.PAR
21 HBEN
20
CS
19
RD
18 Three-State Data Output/Data Output in serial modeD7/DOUT
13 Three-State Data OutputsD2/D10
14 Three-State Data Outputs: MSB = D11D3/D11
15 Three-State Data OutputD4
16 Three-State Data Output/Serial Strobe Output in serial modeD5/SSTRB
17 Three-State Data Output/Serial Clock Output in serial mode
10 Three-State Data Outputs: LSB = D0D0/D8
11 Three-State Data OutputsD1/D9
12 Digital GroundDGND
Power-Down Input. A logic low at PD deactivates the ADC—only the bandgap reference is active. A logic
high selects normal operation, internal-reference compensation mode. An open-circuit condition selects
normal operation, external-reference compensation mode.
PIN
9
8
6
BUSY Output is low during a conversion.BUSY
BIP = low selects unipolar mode
BIP = high selects bipolar mode (see Gain and Offset Adjustment section)
BIP
5
4
3
Reference Adjust. Connect to V
DD
to use an extended reference at VREF.REFADJ
Reference-Buffer Output for Internal Reference. Input for external reference when REFADJ is connected to
V
DD
.
VREF
Analog Input Return. Pseudo-differential (see Gain and Offset Adjustment section).AIN-
2
1
Sampled Analog InputAIN+
Negative Supply, 0V to -5.25VV
SS
PD
FUNCTION
NAME