Datasheet
MAX191
between FFE (hex) and FFF (hex). Because interaction
occurs between adjustments, offset should be adjusted
before gain. For an input gain of two, remove R7 and R8.
The MAX191 accepts input voltages from AGND to V
DD
while operating from a single supply, and V
SS
to V
DD
when operating from dual supplies. Figure 22 shows
the bipolar input transfer function with AIN- connected
to midscale for single-supply operation and connected
to GND operating from dual supplies. When operating
from a single supply, the MAX191 can be configured
for bipolar operation on its pseudo-differential input.
Instead of using AIN- as an analog input return, AIN-
can be set to a different positive potential voltage
above ground (BIP pin is set high). The sampled ana-
log input (AIN+) can swing to any positive voltage
above and below AIN-, and the ADC performs bipolar
conversions with respect to AIN-. When operating from
dual supplies, the MAX191 full-scale range is from
-V
REF
/2 to +V
REF
/2.
Digital Bus Noise
If the data bus connected to the ADC is active during a
conversion, crosstalk from the data pins to the ADC
comparator may generate errors. Slow-memory mode
avoids this problem by placing the µP in a wait state
during the conversion. In ROM mode, if the data bus is
active during the conversion, it should be isolated from
the ADC using three-state drivers.
The ADC generates considerable digital noise in ROM
mode when RD or CS go high and the output data dri-
vers are disabled after a conversion has started. This
noise can cause large errors if it occurs when the SAR
latches a comparator decision. To avoid this problem,
RD and CS should be active for less than one clock
cycle. If this is not possible, RD or CS should go high at
the rising edge of CLK, since the comparator output is
always latched on falling edges of CLK.
Layout, Grounding, Bypassing
Use printed circuit boards for best system performance.
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
20 ______________________________________________________________________________________
RD
0
OPEN CIRCUIT (FLOAT)
PD
12.5µs
2ms
VREF
200ms
Figure 19b. Low Average-Power Mode Operation (External
Compensation)
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
0 1 2 3
FS
FS–1LSB
OUTPUT
CODE
FULL-SCALE
TRANSITION
FS = VREF
1LSB =
4096
FS
AIN INPUT VOLTAGE (LSB)
Figure 20. Unipolar Transfer Function
V
IN
R3
10k
R1
100Ω
R2
49.9Ω
R4
10k
TO AIN+
MAX480
Figure 21a. Trim Circuit for Gain (±0.5%)