Datasheet

MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
12 ______________________________________________________________________________________
HBEN
CLK
CS
RD
BUSY
DATA
HOLD*
TRACK
t
8
t
1
t
4
t
5
t
2
t
CONV
t
12
t
3
t
7
t
3
t
7
t
10
t
9
t
8
*INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High
NEW DATA
D7–D0
NEW DATA
D11–D8
t
7
t
3
OLD DATA
D7–D0
Figure 9. ROM Mode Timing, Reading Data without Starting a Conversion
SCLK
OUT
SCLK
CS
SSTRB
DOUT
t
20
t
20
t
22
t
16
t
23
t
14
t
15
t
22
t
21
t
19
THREE STATE
THREE STATE
t
23
t
17
t
12
12 SCLK CYCLES
HOLD
TRACK
THREE STATE
THREE STATE
Figure 10. Serial-Interface Mode Timing Diagram (RD = low)