Datasheet
MAX1917
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
12 ______________________________________________________________________________________
high-side FET from turning on until DL is fully off. There
must be a low-resistance, low-inductance path from the
DL driver to the MOSFET gate in order for the adaptive
dead-time circuit to work properly. Otherwise, the
sense circuitry in the MAX1917 interprets the MOSFET
gate as off while there is actually still charge left on the
gate. Use very short, wide traces measuring 10
squares to 20 squares (50mils to 100mils wide if the
MOSFET is 1in from the MAX1917). The dead time at
the other edge (DH turning off) is determined by a fixed
35ns (typ) internal delay. The internal pulldown transis-
tor that drives DL low is robust, with a 0.5Ω (typ) on-
resistance. This helps prevent DL from being pulled up
during the fast rise time of the inductor node, due to
capacitive coupling from the drain to the gate of the
massive low-side synchronous-rectifier MOSFET. Some
combinations of high- and low-side FETs may be
encountered that cause excessive gate-drain coupling,
which can lead to efficiency-killing, EMI-producing
shoot-through currents. This can often be remedied by
adding a resistor (R
BST
) in series with BST, which
increases the turn-on time of the high-side FET without
degrading the turn-off time (Figure 2).
POK
V+
DDR
EN/HSD
REF
GND
ILIM
VTT
VTTR
PGND
VL
BST
DH
LX
DL
FSEL
2.5V
C2
2 x 330µF
6V
C1
1µF
6.3V
C8
0.47µF/10V
V+
V
DDR
PGND
C3
4.7µF
10V
C4
0.47µF
10V
C7
1µF/6.3V
C9
0.47µF/25V
2.5V
5.5V TO 14V
1.25V AT 7A
L1
0.68µH/9A
Q2
IRF7463
Q1
IRF7463
D1
CMPSH-3
Q3
2N7002K
R3
20kΩ
R2
5.1kΩ
VL
VL
SHDN
POK
VL
OUTPUT CAPACITORS ARE SELECTED TO COMPLY WITH JEDEC SPECIFICATIONS.
C6
6 x 270µF
2V
C5
2 x 10µF
6.3V
V
OUT
V
IN
VTTR
MAX1917
3
10
2
1
7
5
6
8
11
14
15
16
12
13
4
9
Figure 3. Typical Application Circuit for 1.25V at 7A Output
Typical Application Circuits