Datasheet

MAX1875/MAX1876
An R
ILIM
resistance range of 100kΩ to 600kΩ corre-
sponds to a current-limit threshold of 50mV to 300mV.
When adjusting the current limit, 1% tolerance resistors
minimize error in the current-limit threshold.
For foldback current limit, a resistor (R
FBI
) is added
from ILIM pin to output. The value of R
ILIM
and R
FBI
can then be calculated as follows:
First select the percentage of foldback, P
FB
, from 15%
to 30%, then:
Input Capacitor
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor must meet the ripple current
requirement (I
RMS
) imposed by the switching currents
as defined by the following equation:
I
RMS
has a maximum value when the input voltage
equals twice the output voltage (V
IN
= 2V
OUT
), so
I
RMS(MAX)
= I
LOAD
/ 2. For most applications, non-
tantalum capacitors (ceramic, aluminum, polymer, or
OS-CON) are preferred at the input due to their robust-
ness with high inrush currents typical of systems that
can be powered from very low impedance sources.
Additionally, two (or more) smaller-value low-ESR capac-
itors can be connected in parallel for lower cost. Choose
an input capacitor that exhibits less than +10°C temper-
ature rise at the RMS input current for optimal long-term
reliability.
Output Capacitor
The key selection parameters for the output capacitor
are capacitance value, ESR, and voltage rating. These
parameters affect the overall stability, output ripple volt-
age, and transient response. The output ripple has two
components: variations in the charge stored in the out-
put capacitor, and the voltage drop across the capaci-
tor’s ESR caused by the current flowing into and out of
the capacitor:
The output voltage ripple as a consequence of the ESR
and output capacitance is:
where I
P-P
is the peak-to-peak inductor current (see the
Inductor Selection section). These equations are suit-
able for initial capacitor selection, but final values
should be verified by testing in a prototype or evaluation
circuit.
VIR
V
I
Cf
I
VV
fL
V
V
RIPPLE ESR P P ESR
RIPPLE C
PP
OUT SW
PP
IN OUT
SW
OUT
IN
()
()
=
=
=












-
-
-
-
8
VV V
RIPPLE RIPPLE ESR RIPPLE C
≅+
() ()
II
VVV
V
RMS LOAD
OUT IN OUT
IN
=
()-
R
PV
P
and
R
VPR
VVP
FBI
FB OUT
FB
ILIM
ITH FB FBI
OUT ITH FB
=
×
×
=
××
×
[]
510 1
10 1
10 1
6-
-
-
--
()
()
()
Dual 180° Out-of-Phase PWM Step-
Down Controllers with POR
14 ______________________________________________________________________________________
MAX1875
OUT_
R_A
R_B
FB_
V
OUT_
> 1V
MAX1875
OUT_
R_C
R_A
FB_
REF
V
OUT_
< 1V
Figure 6. Adjustable Output Voltage