Datasheet

Detailed Description
DC-DC PWM Controller
The MAX1858 step-down converters use a PWM volt-
age-mode control scheme (Figure 2) for each out-of-
phase controller. The controller generates the clock
signal by dividing down the internal oscillator or SYNC
input when driven by an external clock, so each con-
troller’s switching frequency equals half the oscillator
frequency (f
SW
= f
OSC
/2). An internal transconductance
error amplifier produces an integrated error voltage at
the COMP pin, providing high DC accuracy. The volt-
age at COMP sets the duty cycle using a PWM com-
parator and a ramp generator. At each rising edge of
the clock, REG1’s high-side N-channel MOSFET turns
on and remains on until either the appropriate duty
cycle or until the maximum duty cycle is reached.
REG2 operates out-of-phase, so the second high-side
MOSFET turns on at each falling edge of the clock.
During each high-side MOSFET’s on-time, the associat-
ed inductor current ramps up.
During the second-half of the switching cycle, the high-
side MOSFET turns off and the low-side N-channel
MOSFET turns on. Now the inductor releases the stored
energy as its current ramps down, providing current to
the output. Under overload conditions, when the induc-
tor current exceeds the selected valley current-limit
(see the Current-Limit Circuit (ILIM_) section), the high-
side MOSFET does not turn on at the appropriate clock
edge and the low-side MOSFET remains on to let the
inductor current ramp down.
Synchronized Out-of-Phase Operation
The two independent regulators in the MAX1858 oper-
ate 180° out-of-phase to reduce input filtering require-
ments, reduce electromagnetic interference (EMI), and
improve efficiency. This effectively lowers component
cost and saves board space, making the MAX1858
ideal for cost-sensitive applications.
Dual-switching regulators typically operate both con-
trollers in-phase, and turn on both high-side MOSFETs
at the same time. The input capacitor must then sup-
port the instantaneous current requirements of both
controllers simultaneously, resulting in increased ripple
voltage and current when compared to a single switch-
ing regulator. The higher RMS ripple current lowers effi-
ciency due to power loss associated with the input
capacitor’s effective series resistance (ESR). This typi-
cally requires more low-ESR input capacitors in parallel
to minimize input voltage ripple and ESR-related loss-
es, or to meet the necessary ripple-current rating.
MAX1858
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
_______________________________________________________________________________________ 7
Pin Description (continued)
PIN NAME FUNCTION
14 DH1 High-Side Gate Driver Output for Regulator 1 (REG1). DH1 swings from LX1 to BST1.
15 LX1
External Inductor Connection for Regulator 1 (REG1). Connect LX1 to the switched side of the
inductor. LX1 serves as the lower supply rail for the DH1 high-side gate driver.
16 BST1
Boost Flying-Capacitor Connection for Regulator 1 (REG1). Connect BST1 to an external ceramic
capacitor and diode according to Figure 1.
17 DL1 Low-Side Gate-Driver Output for Regulator 1 (REG1). DL1 swings from PGND to V
L
.
18 PGND Power Ground
19 V
L
Internal 5V Linear-Regulator Output. Supplies the regulators and powers the low-side gate drivers
and external boost circuitry for the high-side gate drivers.
20 DL2 Low-Side Gate-Driver Output for Regulator 2 (REG2). DL2 swings from PGND to V
L
.
21 BST2
Boost Flying-Capacitor Connection for Regulator 2 (REG2). Connect BST2 to an external ceramic
capacitor and diode according to Figure 1.
22 LX2
External Inductor Connection for Regulator 2 (REG2). Connect LX2 to the switched side of the
inductor. LX2 serves as the lower supply rail for the DH2 high-side gate driver.
23 DH2 High-Side Gate-Driver Output for Regulator 2 (REG2). DH2 swings from LX2 to BST2.
24 EN
Active-High Enable Input. A logic low shuts down both controllers. Connect to V
L
for always-on
operation.