Datasheet

All four N-channel MOSFETs must be a logic-level type
with guaranteed on-resistance specifications at V
GS
≥
4.5V. For maximum efficiency, choose a high-side
MOSFET (N
H
_) that has conduction losses equal to the
switching losses at the optimum input voltage. Check to
ensure that the conduction losses at minimum input
voltage do not exceed MOSFET package thermal limits,
or violate the overall thermal budget. Also, check to
ensure that the conduction losses plus switching losses
at the maximum input voltage do not exceed package
ratings or violate the overall thermal budget.
Ensure that the MAX1858 DL _ gate driver can drive
N
L
_. In particular, check that the dv/dt caused by N
H
_
turning on does not pull up the N
L
_ gate through N
L
_’s
drain-to-gate capacitance. This is the most frequent
cause of cross-conduction problems.
Gate-charge losses are dissipated by the driver and do
not heat the MOSFET. All MOSFETs must be selected
so that their total gate charge is low enough that V
L
can
power all four drivers without overheating the IC:
MOSFET package power dissipation often becomes a
dominant design factor. I
2
R power losses are the great-
est heat contributor for both high-side and low-side
MOSFETs. I
2
R losses are distributed between N
H
_ and
N
L
_ according to duty factor as shown in the equations
below. Switching losses affect only the high-side
MOSFET, since the low-side MOSFET is a zero-voltage
switched device when used in the buck topology.
Calculate MOSFET temperature rise according to pack-
age thermal-resistance specifications to ensure that
both MOSFETs are within their maximum junction tem-
perature at high ambient temperature. The worst-case
dissipation for the high-side MOSFET (P
NH
) occurs at
both extremes of input voltage, and the worst-case dis-
sipation for the low-side MOSFET (P
NL
) occurs at maxi-
mum input voltage.
I
GATE
is the average DH driver output current capability
determined by:
where R
DS(ON)DH
is the high-side MOSFET driver’s on-
resistance (5Ω max), and R
GATE
is any series resis-
tance between DH and BST (Figure 3).
where P
NH(CONDUCTION)
is the conduction power loss
in the high-side MOSFET, and P
NL
is the total low-side
power loss.
To reduce EMI caused by switching noise, add a 0.1µF
ceramic capacitor from the high-side switch drain to
the low-side switch source or add resistors in series
with DL_ and DH_ to increase the MOSFETs’ turn-on
and turn-off times.
Applications Information
Dropout Performance
When working with low input voltages, the output-voltage
adjustable range for continuous-conduction operation is
restricted by the minimum off-time (t
OFF(MIN)
). For best
dropout performance, use the lowest (100kHz) switching-
frequency setting. Manufacturing tolerances and internal
propagation delays introduce an error to the switching
frequency and minimum off-time specifications. This error
is more significant at higher frequencies. Also, keep in
mind that transient response performance of buck regula-
tors operated close to dropout is poor, and bulk output
PIR
V
V
PP P
PI R
V
V
NH CONDUCTION LOAD DS ON NH
OUT
IN
NH TOTAL NH SWITCHING NH CONDUCTION
NL LOAD DS ON NL
OUT
IN
()()
()( )( )
()
=






=+
=












2
2
1-
I
V
RR
GATE
L
DS ON DH GATE
=
+
()
2
()
P
VI f Q Q
I
NH SWITCHING
IN LOAD OSC GS GD
GATE
()
=
+






2
PVQ f
VL IN G TOTAL SW
=× ×
_
MAX1858
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
______________________________________________________________________________________ 17
BODE PLOT FOR VOLTAGE-
MODE CONTROLLERS
FREQUENCY (MHz)
GAIN (dB)
0.10.01
-40
-30
-20
-10
0
10
20
30
40
50
0.001 1
f
Z-COMP_A
f
COMP_B
f
LC
f
CO
f
ESR
f
SWITCH
Figure 8. Voltage-Mode Loop Analysis