Datasheet

removed from the output filter capacitors by a sudden
load step. The amount of output-voltage sag is also a
function of the maximum duty factor, which can be cal-
culated from the minimum off-time and switching fre-
quency:
where t
OFF(MIN)
is the minimum off-time (see the
Electrical Characteristics), and f
SW
is set by R
OSC
(see
the Setting the Switching Frequency section).
Compensation
Each voltage-mode controller section employs a
transconductance error amplifier whose output is the
compensation point of the control loop. The control
loop is shown in Figure 7. For frequencies much lower
than Nyquist, the PWM block can be simplified to a
voltage amplifier. Connect R
COMP_
and C
COMP_A
from
COMP to GND to compensate the loop (see Figure 7).
The inductor, output capacitor, compensation resistor,
and compensation capacitors determine the loop sta-
bility. Since the inductor and output capacitor are cho-
sen based on performance, size, and cost, select the
compensation resistor and capacitors to optimize con-
trol-loop stability.
To determine the loop gain (A
L
), consider the gain from
FB to COMP (A
COMP/FB
), from COMP to LX
(A
LX/COMP
), and from LX to FB (A
FB/LX
). The total loop
gain is:
where:
assuming an ideal integrator, and assuming that
C
COMP_B
is much less than C
COMP_A
.
for frequencies lower than Nyquist.
Therefore:
For an ideal integrator, this loop gain approaches infini-
ty at DC. In reality the g
M
amplifier has a finite output
impedance which imposes a finite, but large, loop gain.
It is this large loop gain that provides DC load accura-
cy. The dominant pole occurs due to the integrator, and
for this analysis, it can be approximated to occur at DC.
R
COMP
creates a zero at:
The inductor and capacitor form a double pole at:
At some higher frequency the output capacitor’s
impedance becomes insignificant compared to its ESR,
and the LC system becomes more like an LR system,
turning a double pole into a single pole. This zero
occurs at:
A final pole is added using C
COMP_B
to reduce the
gain and attenuate noise after crossover. This pole
(f
COMP_B
) occurs at:
Figure 8 shows a Bode plot of the poles and zeros in
their relative locations.
Near crossover the following approximations can be
made to simplify the loop-gain equation:
f
RC
COMP B
COMP COMP B
_
_
=
×
1
2π
f
RC
ESR
ESR OUT
=
×
1
2π
f
LC
LC
OUT
=
×
1
2π
f
RC
Z COMP A
COMP COMP A
__
__
=
×
1
2π
A
g
SC
SR C
SR C
V
V
V
V
SR C
SLC
L
M COMP
COMP A
COMP COMP A
COMP COMP B
IN
RAMP
SET
OUT
ESR OUT
OUT
≅×
+
+
×
××
+
+
_
_
_
_
1
1
1
1
2
A
V
V
V
V
sR C
SLC SR C
V
V
SR C
VSLC
FB LX
FB
LX
SET
OUT
ESR OUT
OUT ESR OUT
SET
OUT
ESR OUT
OUT OUT
/
==
+
++
≅
+
+
1
1
1
1
2
2
A
V
V
V
V
LX COMP
LX
COMP
IN
RAMP
/
==
A
V
V
g
SC
sR C
sR C
COMP FB
COMP
FB
M COMP
COMP
COMP COMP A
COMP COMP B
/
_
_
_
=≅
×
+
+
1
1
AAAA
L COMP FB LX COMP FB LX
=××
// /
V
LI I
V
Vf
t
CV
VV
Vf
t
SAG
LOAD LOAD
OUT
IN SW
OFF MIN
OUT OUT
IN OUT
IN SW
OFF MIN
=






+






















()
()
()
12
2
2
-
-
-
MAX1858
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
______________________________________________________________________________________ 15