Datasheet

MAX1856
Wide Input Range, Synchronizable,
PWM SLIC Power Supply
______________________________________________________________________________________ 13
high side of R
CS
, and connect a 1000pF capacitor
between CS and GND.
Power MOSFET Selection
The MAX1856 drives a wide variety of N-channel power
MOSFETs (NFETs). Since the LDO limits the EXT output
gate drive to no more than 5V, a logic-level NFET is
required. Best performance, especially with input volt-
ages below 5V, is achieved with low-threshold NFETs
that specify on-resistance with a gate-to-source voltage
(V
GS
) of 2.7V or less. When selecting an NFET, key
parameters include:
1) Total gate charge (Q
G
)
2) Reverse transfer capacitance or charge (C
RSS
)
3) On-resistance (R
DS(ON)
)
4) Maximum drain-to-source voltage (V
DS(MAX)
)
5) Minimum threshold voltage (V
TH(MIN)
)
At high switching rates, dynamic characteristics (para-
meters 1 and 2 above) that predict switching losses
may have more impact on efficiency than R
DS(ON)
,
which predicts DC losses. Q
G
includes all capacitance
associated with charging the gate. In addition, this
parameter helps predict the current needed to drive the
gate at the selected operating frequency. The continu-
ous LDO current for the FET gate is:
For example, the IRLL2705 has a typical Q
G
of 17nC
(at V
GS
= 5V); therefore, the I
GATE
current at 500kHz is
8.5mA.
The switching element in a flyback converter must have
a high enough voltage rating to handle the input volt-
age plus the reflected secondary voltage, as well as
any spikes induced by leakage inductance. The reflect-
ed secondary voltage is given by:
where V
DIODE
is the voltage drop across the output
diode. For a 10% variation in input voltage and a 30%
safety margin, this gives a required 33V voltage rating
(V
DS
) for the switching MOSFET in Figure 1. The
IRLL2705 with a V
DS
of 55V was chosen.
Diode Selection
The MAX1856’s high switching frequency demands a
high-speed rectifier. Schottky diodes are recommend-
ed for most applications because of their fast recovery
time and low forward voltage. Ensure that the diode’s
average current rating exceeds the peak secondary
current, using the diode manufacturer’s data or approx-
imating it with the following formula:
where N = N
s
/N
P
is the secondary-to-primary turns
ratio. Additionally, the diode’s reverse breakdown volt-
age must exceed V
OUT
plus the reflected input voltage
plus the leakage inductance spike. For high output volt-
ages (50V or above), Schottky diodes may not be prac-
tical because of this voltage requirement. In these
cases, use a faster ultra-fast recovery diode with ade-
quate reverse-breakdown voltage.
Capacitor Selection
Output Filter Capacitor
The output capacitor (C
OUT
) does all the filtering in a fly-
back converter. Typically, C
OUT
must be chosen based
on the output ripple requirement. The output ripple is
due to the variations in the charge stored in the output
capacitor with each pulse and the voltage drop across
the capacitor’s equivalent series resistance (ESR)
caused by the current into and out of the capacitor. The
ESR-induced ripple usually dominates, so output capac-
itor selection is actually based upon the capacitor’s
ESR, voltage rating, and ripple current rating.
Input Filter Capacitor
The input capacitor (C
IN
) in flyback designs reduces
the current peaks drawn from the input supply and
reduces noise injection. The value of C
IN
is largely
determined by the source impedance of the input sup-
ply. High source impedance requires high input capac-
itance, particularly as the input voltage falls. Since
inverting flyback converters act as “constant-power”
loads to their input supply, input current rises as the
input voltage falls. Consequently, in low-input-voltage
designs, increasing C
IN
and/or lowering its ESR can
add as much as 5% to the conversion efficiency.
Bypass Capacitors
In addition to C
IN
and C
OUT
, three ceramic bypass
capacitors are also required with the MAX1856. Bypass
REF to GND with 2.2µF or more. Bypass LDO to GND
with 1µF or more. And bypass V
CC
to GND with 1µF or
more. All bypass capacitors should be located as close
to their respective pins as possible.
Compensation Capacitor
Output ripple voltage due to C
OUT
ESR affects loop
stability by introducing a left half-plane zero. A small
capacitor connected from FB to GND forms a pole with
II
V
NV
I
N
D PK OUT
OUT
IN
L
()
=+
×






+
∆
1
2
V
N
N
VV
REFLECT
P
S
OUT DIODE
=+
()
IQ
GATE G OSC
=׃