Datasheet

MAX17595/MAX17596/MAX17597
Peak-Current-Mode Controllers for
Flyback and Boost Regulators
9Maxim Integrated
Pin Description
Pin Configuration
PIN NAME FUNCTION
1, 12 N.C. No Connection
2 SLOPE
Slope Compensation Input. A resistor, R
SLOPE
, connected from SLOPE to SGND programs the
amount of slope compensation with reference-voltage soft-start mode. Connecting this pin to
SGND enables duty-cycle soft-start with default slope compensation of 50mV/Fs. Setting V
SLOPE
>
4V enables reference voltage soft-start with default slope compensation of 50mV/Fs.
3 RT
Switching Frequency Programming Resistor Connection. Connect resistor R
RT
from RT to SGND to
set the PWM switching frequency.
4 DITHER/SYNC
Frequency Dithering Programming or Synchronization Connection. For spread-spectrum frequency
operation, connect a capacitor from DITHER to SGND, and a resistor from DITHER to RT. To
synchronize the internal oscillator to the externally applied frequency (MAX17595/MAX17596 only),
connect DITHER/SYNC to the synchronization pulse.
5 COMP
Transconductance Amplifier Output. Connect the frequency compensation network between
COMP and SGND.
6 FB Transconductance Amplifier Inverting Input
7 SS
Soft-Start Capacitor Pin for Flyback Regulator. Connect a capacitor C
SS
from SS to SGND to set
the soft-start time interval.
8 SGND Signal Ground. Connect SGND to the signal ground plane.
9 CS Current-Sense Input. Peak-current-limit trip voltage is 300mV (typ).
10 PGND Power Ground. Connect PGND to the power ground plane.
11 NDRV External Switching nMOS Gate-Driver Output
15
16
14
13
5
6
7
RT
DITHER /
SYNC
8
N.C.
PGND CS N.C.
13
V
IN
4
12 10 9
EN / UVLO
OVI
EP
SGND
SS
FB
COMP
SLOPE NDRV
2
11
V
DRV
TQFN
MAX17595
MAX17596
TOP VIEW
+
15
16
14
13
5
6
7
RT
DITHER
8
N.C.
PGND CS N.C.
13
V
IN
4
12 10 9
EN /UVLO
OVI
EP
SGND
SS
FB
COMP
SLOPE NDRV
2
11
V
DRV
TQFN
MAX17597
+