Datasheet
MAX17502 60V, 1A, Ultra-Small, High-Efciency,
Synchronous Step-Down DC-DC Converter
www.maximintegrated.com
Maxim Integrated
│
13
Figure 1. Setting the Output Voltage
Figure 2. Adjustable EN/UVLO Network
Adjusting Output Voltage
The MAX17502E and MAX17502F have preset output
voltagesof3.3Vand5.0V,respectively.ConnectFB/VO
directly to the positive terminal of the output capacitor
(see the Typical Applications Circuits).
The MAX17502G/H offer an adjustable output voltage
from 0.9V to 92%V
IN
. Set the output voltage with a resis-
tive voltage-divider connected from the positive terminal
of the output capacitor (V
OUT
) toGND (see Figure 1).
Connect the center node of the divider to FB/VO. To
optimizeefficiencyandoutputaccuracy,usethefollowing
proceduretochoosethevaluesofR4andR5:
For MAX17502G, select the parallel combination of R4
andR5,Rptobelessthan15kΩ.FortheMAX17502H,
selectthe parallelcombination of R4and R5,Rpto be
lessthan30kΩ.OnceRpisselected,calculateR4as:
OUT
Rp V
R4
0.9
×
=
CalculateR5asfollows:
OUT
R4 0.9
R5
(V - 0.9)
×
=
Setting the Input Undervoltage Lockout Level
The device offers an adjustable input undervoltage-
lockout level. Set the voltage at which the device turns
on with a resistive voltage-divider connected from V
IN
toGND(seeFigure 2). Connect the center node of the
divider to EN/UVLO.
ChooseR1tobe3.3MΩ,andthencalculateR2as:
INU
R1 1.218
R2
(V -1.218)
×
=
where V
INU
is the voltage at which the device is required
to turn on. For adjustable output voltage devices, ensure
that V
INU
is higher than 0.8 x V
OUT
.
External Loop Compensation for Adjustable
Output Versions
The MAX17502 uses peak current-mode control scheme
andneeds only a simple RCnetwork tohave astable,
high-bandwidth control loop for the adjustable output volt-
age versions. The basic regulator loop is modeled as a
power modulator, an output feedback divider, and an error
amplifier.ThepowermodulatorhasDCgainG
MOD(dc)
,
withapoleandzeropair.Thefollowingequationdefines
the power modulator DC gain:
MOD(dc )
LOAD IN SW SEL
2
G
1 0.4 0.5 - D
R VfL
=
++
×
where R
LOAD
= V
OUT
/I
OUT(MAX)
, f
SW
is the switching
frequency, L
SEL
is the selected output inductance, D is
the duty ratio, D = V
OUT/
V
IN
.
The compensation network is shown in Figure 3.
R
Z
can be calculated as:
Z C SEL OUT
R 6000 f C V= ×× ×
whereR
Z
isinΩ.Choosef
C
to be 1/12th of the switching
frequency.
C
Z
can be calculated as follows:
SEL MOD(dc)
Z
Z
CG
C
R
×
=
C
P
can be calculated as follows:
=
π× ×
P
Z SW
1
C - 5pF
Rf
Figure 3. External Compensation Network
R5
R4
FB/VO
GND
V
OUT
R2
R1
EN/UVLO
GND
V
IN
R
Z
TO COMP PIN
C
Z
C
P










