Datasheet

MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
22Maxim Integrated
( )
2
2
SEC
SECRMS SECPEAK SECPEAK SEC
2
MAX
I
II I I
3
1D

∆

= + − ×∆


×−
where DI
SEC
is the ripple current in the secondary current
waveform, and is given by:
INMIN MAX
SEC
PRI SW
VD
I
L fK

×
∆=

××

Current-limit setting the peak current can be calculated
as follows:
LIMF PRIPEAK
I I 1.2= ×
Primary RCD Snubber Selection
The design procedure for RCD snubber selection is iden-
tical to that outlined in the DCM Flyback section.
Output-Capacitor Selection
X7R ceramic output capacitors are preferred in industrial
applications due to their stability over temperature. The
output capacitor is usually sized to support a step load
of 50% of the maximum output current in the application,
such that the output-voltage deviation is contained to 3%
of the output-voltage change. The output capacitance
can be calculated as:
STEP RESPONSE
OUTF
OUTF
It
C
V
×
=
∆
RESPONSE
C SW
0.33 1
t ()
ff
≅+
where I
STEP
is the load step, t
RESPONSE
is the response
time of the controller, DV
OUTF
is the allowable output
voltage deviation, and f
C
is the target closed-loop cross-
over frequency. f
C
is chosen to be less than 1/5 of the
worst-case (lowest) RHP zero frequency (f
RHP
). The right
half-plane zero frequency is calculated as:
2
MAX OUTF
ZRHP
2
MAX PRI OUTF
(1 D ) V
f
2D LI K
−×
=
×π× × × ×
For the CCM flyback converter, the output capacitor
supplies the load current when the main switch is on,
and therefore the output-voltage ripple is a function of
load current and duty cycle. Use the following equation
to estimate the output-voltage ripple:
OUTF MAX
COUTF
SW OUTF
ID
V
fC
×
∆=
×
Input-Capacitor Selection
The design procedure for input capacitor selection is
identical to that outlined in the DCM Flyback section.
External MOSFET Selection
The design procedure for external MOSFET selection is
identical to that outlined in the DCM Flyback section.
Secondary Diode Selection
The design procedure for secondary diode selection is
identical to that outlined in the DCM Flyback section.
Error-Amplifier Compensation Design
In the CCM flyback converter, the primary inductance
and the equivalent load resistance introduces a right
half-plane zero at the following frequency:
2
MAX OUTF
ZRHP
2
MAX PRI OUTF
(1 D ) V
f
2D LI K
−×
=
×π× × × ×
The loop-compensation values are calculated as:
( )

×
= × + ×+

−×

2
OUTF
RHP
Z MAX
MAX P
200 I
f
R K1 1 D
(1 D ) 5 f
where f
P
, the pole due to output capacitor and load, is
given by:
MAX OUTF
P
OUTF OUTF
(1 D ) I
f
2C V
+×
=
×π× ×
The above selection sets the loop-gain crossover fre-
quency (f
C
, where the loop gain equals 1) equal to 1/5
the right half-plane zero frequency:
ZRHP
C
f
f
5
≤
With the control-loop zero placed at the load pole fre-
quency:
Z
ZP
1
C
2R f
=
π× ×
With the high-frequency pole placed at 1/2 the switching
frequency:
P
Z SW
1
C
Rf
=
π× ×