Datasheet

MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
14Maxim Integrated
Spread-Spectrum Factory Option
For EMI-sensitive applications, a spread-spectrum-
enabled version of the device can be requested from
the factory. The frequency-dithering feature modulates
the switching frequency by Q10% at a rate of 1/16 the
switching frequency. This spread-spectrum-modulation
technique spreads the energy of switching-frequency
harmonics over a wider band while reducing their peaks,
helping to meet stringent EMI goals.
Applications Information
Startup Voltage and Input Overvoltage-
Protection Setting (EN/UVLO, OVI)
The devices’ EN/UVLO pin serves as an enable/disable
input, as well as an accurate programmable input UVLO
pin. The devices do not commence startup operations
unless the EN/UVLO pin voltage exceeds 1.23V (typ).
The devices turn off if the EN/UVLO pin voltage falls
below 1.17V (typ). A resistor-divider from the input DC
bus to ground can be used to divide down and apply a
fraction of the input DC voltage (V
DC
) to the EN/UVLO
pin. The values of the resistor-divider can be selected
such that the EN/UVLO pin voltage exceeds the 1.23V
(typ) turn-on threshold at the desired input DC bus volt-
age. The same resistor-divider can be modified with an
additional resistor (R
OVI
) to implement input overvoltage
protection in addition to the EN/UVLO functionality, as
shown in Figure 3. When voltage at the OVI pin exceeds
1.23V (typ), the devices stop switching and resume
switching operations only if voltage at the OVI pin falls
below 1.17V (typ). For given values of startup DC input
voltage (V
START
), and input overvoltage-protection volt-
age (V
OVI
), the resistor values for the divider can be cal-
culated as follows, assuming a 24.9kI resistor for R
OVI
:
OVI
EN OVI
START
V
R R 1k
V

= × −Ω


where R
OVI
is in kI and V
START
and
V
OVI
are in volts.
START
SUM OVI EN
V
R R R 1k
1.23

= + × −Ω




where R
EN
and
R
OVI
are in kI and V
START
is in volts.
R
SUM
may need to be implemented as equal multiple resistors
in series (
R
DC1
,
R
DC2
,
R
DC3
) such that voltage across each
resistor is limited to its maximum operating voltage.
= = = Ω
SUM
DC1 DC2 DC3
R
RR R k
3
Figure 2. Sequencing of MAX17497A/MAX17497B Output Voltage Rails
EN/UVLO
6.5V
t
SSF
t
SSB
RESETN
t
RESETN
4ms
95%
92%
V
OUTB
V
OUTF
95%