Datasheet

Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
MAX17122
______________________________________________________________________________________ 33
the boost-buck regulator, the high-current input loop
goes from the positive terminal of the input capacitor
to the IC’s LX3 pin, inductor, out of GND1, and to the
input capacitor’s negative terminal. The high-current
output loop is from the ground terminal to inductor,
to the IC’s LX3 pin, to the output diode (D3), the
negative terminal of the output capacitor, reconnect-
ing between the output capacitor/input capacitor
ground terminals. Connect these loop components
with short, wide connections. Avoid using vias in the
high-current paths. If vias are unavoidable, use many
vias in parallel to reduce resistance and inductance.
U Create a power ground island for the step-down
regulator, consisting of the input and output capaci-
tor grounds and the diode ground. Connect all these
together with short, wide traces or a small ground
plane. Similarly, create a power ground island (GND1)
for the step-up regulator, consisting of the input and
output capacitor grounds and the GND1 pin. Create
a power ground island for the boost-buck regulator,
consisting of the input and output capacitor grounds
and inductor ground. Connect the step-down regula-
tor ground plane, GND1 ground plane, boost-buck
ground plane, charge-pump power ground, and
negative linear-regulator power ground together with
wide traces. Maximizing the width of the power
ground traces improves efficiency and reduces out-
put voltage ripple and noise spikes.
U Create an analog ground plane (AGND) consisting
of the AGND pin, all the feedback-divider ground
connections, the COMP1, COMP3, DEL, SS, DLY1,
DLY2, EN1, and EN2 capacitor ground connections,
and the device’s exposed backside pad. Connect
the GND1 and AGND islands by connecting the two
ground pins directly to the exposed backside pad.
Make no other connections between these separate
ground planes.
U Place all feedback voltage-divider resistors as close
as possible to their respective feedback pins. The
divider’s center trace should be kept short. Placing
the resistors far away causes their FB traces to
become antennas that can pick up switching noise.
Care should be taken to avoid running any feedback
trace near LX1, LX2, and LX3.
U Place IN pin, IN2 pin, and VL pin bypass capaci-
tors as close as possible to the device. The ground
connection of the VL bypass capacitor should be
connected directly to the AGND pin with a wide trace.
U Minimize the length and maximize the width of the
traces between the output capacitors and the load for
best transient responses.
U Minimize the size of the LX1, LX2, and LX3 nodes
while keeping them wide and short. Keep the LX1,
LX2, and LX3 nodes away from feedback nodes
(FB1, FB2, FB3, FBP, and FBN) and analog ground.
Use DC traces as a shield if necessary.
Refer to the MAX17122 evaluation kit data sheet for an
example of proper board layout.
Pin Configuration
THIN QFN
6mm x 6mm
MAX17122
TOP VIEW
5
6
4
3
22
21
23
DLY1
24
GPGD
LX1 VL COMP1 LX1 GND1 GND1 FB1 RHVS
11 12
IN2
14 15 16 17
37383940 36 34 33 32
AGND
LX2
COMP3
FB3
NTC
SET
EN1
N.C.
13
35
7
LX2
AGND
8
9
10
BST2
OUTB
FB2
DEL
RESET
DRVP
IN2
2
25
N.C.
IN
1
26
27
28
29
30
LX3
EN2
IN3
18 19 20
31
GATE
+
HVS
FBN
SS
DRVN
DLY2
FBP