Datasheet

Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
MAX17122
32 _____________________________________________________________________________________
The transistor’s saturation voltage at the maximum output
current determines the minimum input-to-output volt-
age differential that the regulator can support. Also, the
package’s power dissipation limits the usable maximum
input-to-output voltage differential. The maximum power-
dissipation capability of the transistor’s package and
mounting must exceed the actual power dissipated in
the device. The power dissipated equals the maximum
charge current (I
CP_DC(MAX)
) multiplied by the maxi-
mum input-to-output voltage differential:
CP_DC(MAX) PNP
P I V= ×
where V
PNP
is the voltage across the pnp emitter and
collector and can be calculated as:
PNP INCP GON POS AVDD D
V V - (V - (V - 2V ))= η
where I
CP_DC(MAX)
is the maximum average DC input cur-
rent of the pnp pass transistor and can be estimated as:
GON D
CP_DC(MAX) LOAD
GON POS AVDD D D
V V
I I
V - (V - 2V ) V
+
≈ ×
η +
where I
LOAD
is the charge pump average DC load current.
A collector capacitor (CP) can increase the current injec-
tion to the step-up regulator switching node, LX1, and
should be avoided unless stable operation of the charge
pump cannot be achieved otherwise. If installed, the
capacitor value should be 0.1FF.
Negative Linear Regulator
Output-Voltage Selection
Adjust the negative linear-regulator output voltage
(GOFF1) by connecting a resistive voltage-divider from
V
GOFF1
to 3.3V with the center tap connected to
FBN (Figure 1). Select R8 in the 20kI to 50kI range.
Calculate R7 with the following equation:
GOFF1 FBN
FBN
V - V
R7 R8
V - 3.3V
= ×
where V
FBN
= 250mV.
Pass-Transistor Selection
The pass transistor must meet specifications for current
gain (h
FEN
), input capacitance, collector-emitter satura-
tion voltage, and power dissipation. The transistor’s cur-
rent gain limits the guaranteed maximum output current to:
BEN
GOFF1(MAX) DRVN FEN(MIN)
BEN
V
I (I - ) h
R
= ×
where I
DRVN
is the minimum guaranteed base-drive
current, V
BEN
is the npn transistor’s base-to-emitter for-
ward voltage drop, and R
BEN
is the pullup resistor con-
nected between the npn transistor’s base and emitter.
Furthermore, the transistor’s current gain increases the
linear regulator’s DC loop gain, so excessive gain desta-
bilizes the output. Therefore, transistors with current gain
over 100 at the maximum output current can be difficult
to stabilize and are not recommended unless the high
gain is needed to meet the load-current requirements.
The transistor’s saturation voltage at the maximum output
current determines the minimum input-to-output voltage
differential that the linear regulator can support. Also, the
package’s power dissipation limits the usable maximum
input-to-output voltage differential. The maximum power-
dissipation capability of the transistor’s package and
mounting must exceed the actual power dissipated in
the device. The power dissipated equals the maximum
load current (I
GOFF1(MAX)
) multiplied by the maximum
input-to-output voltage differential:
GOFF1(MAX) GOFF1(MAX)
P I (-V )= ×
where I
GOFF1(MAX)
is the maximum average DC output
of the negative linear regulator, and V
GOFF1(MAX)
is the
maximum negative output voltage of the linear regulator.
PCB Layout and Grounding
Careful PCB layout is important for proper operation. Use
the following guidelines for good PCB layout:
U Minimize the area of respective high-current loops by
placing each DC-DC converter’s inductor, diode, and
output capacitors near its input capacitors and its
LX_ and power grounds. For the step-down regula-
tor, the high-current input loop goes from the positive
terminal of the input capacitor to the IC’s IN2 pin, out
of LX2, to the inductor, to the positive terminals of the
output capacitors, reconnecting the output capaci-
tor and input capacitor ground terminals. The high-
current output loop is from the inductor to the positive
terminals of the output capacitors, to the negative
terminals of the output capacitors, and to the Schottky
diode (D2). For the step-up regulator, the high-current
input loop goes from the positive terminal of the input
capacitor to the inductor, to the IC’s LX1 pin, out of
GND1, and to the input capacitor’s negative termi-
nal. The high-current output loop is from the positive
terminal of the input capacitor to the inductor, to
the output diode (D1), to the positive terminal of the
output capacitors, reconnecting between the output
capacitor and input capacitor ground terminals. For