Datasheet

Step-Up, Step-Down Regulator, Gate-On Charge Pump,

and Boost-Buck Regulator for TV TFT LCD Display

MAX17122

24 _____________________________________________________________________________________

Power-Up Sequence

The step-down regulator starts up when the MAX17122’s

internal linear-regulator output VL is above its undervolt-

age lockout (UVLO) threshold and EN1 is high. Figure

6 shows the power-up sequence. Once the step-down

regulator soft-start is done, the FB2 fault-detection circuit

is enabled. The step-down regulator power-good timing

control signal (DEL) is enabled after OUTB is above its

designed threshold (see the Step-Down Regulator Power

Good (RESET) section). Once DEL passes above 1.25V,

RESET is passively pulled up high through a resistor. Set

the delay time using the following equation:

DEL

8 A

C DELAY_TIME

1.25V

= ×

The negative linear regulator and the boost-buck regula-

tor are enabled after the step-down regulator finishes its

soft-start and EN2 is high. In the same time, both of the

delay control signals (DLY1 and DLY2) for the step-up

regulator and the positive charge-pump linear regulator

are also enabled.

Figure 6. Power-Up Sequence

UVLO

1.25V

GATE-

1.25V

IN, IN2, IN3

EN1

OUTB

DEL

RESET

VOFF1

GOFF2

EN2

DLY1

DLY2

GON

AVDD

GATE

TIME