Datasheet
Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
MAX17122
20 _____________________________________________________________________________________
where V
AVDD
is the output voltage of the step-up regula-
tor, V
D1
is the voltage drop across diode D1, and V
LX1
is the voltage drop across the internal MOSFET. Figure 3
shows the step-up regulator block diagram.
PWM Controller Block
An error amplifier compares the signal at FB1 to
1.25V and changes the COMP1 output. The voltage
at COMP1 sets the peak inductor current. As the load
varies, the error amplifier sources or sinks current to the
COMP1 output accordingly to produce the inductor peak
current necessary to service the load. To maintain
stability at high duty cycles, a slope-compensation sig-
nal is summed with the current-sense signal.
On the rising edge of the internal clock, the controller
sets a flip-flop, turning on the n-channel MOSFET and
applying the input voltage across the inductor. The
current through the inductor ramps up linearly, storing
energy in its magnetic field. Once the sum of the current-
feedback signal and the slope-compensation exceed
the COMP1 voltage, the controller resets the flip-flop
and turns off the MOSFET. Since the inductor current is
continuous, a transverse potential develops across the
inductor that turns on diode D1. The voltage across the
inductor then becomes the difference between the out-
put voltage and the input voltage. This discharge condi-
tion forces the current through the inductor to ramp back
down, transferring the energy stored in the magnetic
field to the output capacitor and the load. The MOSFET
remains off for the rest of the clock cycle.
Step-Up Regulator External pMOS Pass Switch
As shown in Figure 1, a series external p-channel
MOSFET (Q1) can be installed between the power
supply and inductor L1. This feature is used to sequence
power to AVDD after the MAX17122 has proceeded
through normal startup to limit input surge current during
the output capacitor initial charge, and to provide true
shutdown when the step-up regulator is disabled. When
EN2 is low, GATE is internally pulled up to IN2 through a
25I resistor. Once EN2 is high and the step-down regu-
lator soft-start is finished, DLY1 begins charging. Once
DLY1 is above 1.25V, the GATE starts pulling down with
a 160FA (typ) internal current source. The step-up regu-
lator is enabled and initiates a soft-start routine. When
the gate-source voltage of this external pMOS exceeds
approximately 3V, a boost current of 1mA is added to
quickly complete the charge of GATE capacitance. The
external p-channel MOSFET (Q1) turns on and connects
IN2 to step-up regulator power inductor L1 when GATE
falls below the turn-on threshold of the MOSFET. When
V
GATE
reaches V
IN2
- 5.5V(GATE_OK), LX1 is allowed
to toggle.
Figure 3. Step-Up Regulator Block Diagram
+
-
+
-
+
-
+
-
FB1
GND1
LOGIC AND
DRIVER
ILIM
COMPARATOR
SOFT-
START
CURRENT
SENSE
PWM
COMPARATOR
SLOPE COMP
CLOCK
I
LIMIT
750kHz
OSCILLATOR
TO FAULT LOGIC
FAULT
COMPARATOR
1.25V
COMP1
ERROR
AMP
LX1