Datasheet

Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
MAX17122
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Step-Down Regulator
The step-down regulator consists of an internal n-channel
MOSFET with gate driver, a lossless current-sense net-
work, a current-limit comparator, and a PWM controller
block. The external power stage consists of a Schottky
diode rectifier, an inductor, and output capacitors. The
output voltage is regulated by changing the duty cycle
of the high-side MOSFET. A bootstrap circuit that uses
a 0.1FF flying capacitor between LX2 and BST provides
the supply voltage for the high-side gate driver. Although
the MAX17122 also includes a 10I (typical) low-side
MOSFET, this switch is used to charge the bootstrap
capacitor during startup and maintains fixed-frequency
operation at light load and cannot be used as a synchro-
nous rectifier. An external Schottky diode (D2 in Figure
1) is always required.
PWM Controller Block
The heart of the PWM controller block is a multi-input,
open-loop comparator that sums three signals: the out-
put voltage signal with respect to the reference voltage,
the current-sense signal, and the slope compensation
signal. The PWM controller is a direct-summing type,
lacking a traditional error amplifier and the phase shift
associated with it. This direct-summing configuration
approaches ideal cycle-by-cycle control over the output
voltage.
The step-down controller always operates in fixed-
frequency PWM mode. Each pulse from the oscillator
sets the main PWM latch that turns on the high-side
switch until the PWM comparator changes state. As the
high-side switch turns off, the low-side switch turns on.
The low-side switch stays on until the beginning of the
next clock cycle.
Current Limiting and Lossless Current Sensing
The current-limit circuit turns off the high-side MOSFET
switch whenever the voltage across the high-side
MOSFET exceeds an internal threshold. The actual
current limit is typically 3A.
For current-mode control, an internal lossless sense
network derives a current-sense signal from the inductor
DCR. The time constant of the current-sense network is
not required to match the time constant of the inductor
and has been chosen to provide sufficient current-ramp
signal for stable operation. The current-sense signal is
AC-coupled into the PWM comparator, eliminating most
DC output-voltage variation with load current.
Dual-Mode Feedback
The MAX17122’s step-down regulator supports both
fixed output and adjustable output. Connect FB2 to
AGND to enable the 3.3V fixed output voltage. Connect
a resistive voltage-divider between OUTB and AGND
with the center tap connected to FB2 to adjust the output
voltage. Choose RB (resistance from FB2 to AGND) to
be between 5kI and 50kI, and solve for RA (resistance
from OUTB to FB2) using the following equation:
OUTB
FB2
V
RA RB - 1
V
 
= ×
 
 
where V
FB2
= 1.25V and V
OUTB
may vary from 1.5V to 5V.
Soft-Start
The step-down regulator includes a 7-bit soft-start DAC
that steps its internal reference voltage from 0 to 1.25V in
128 steps. The soft-start period is 3ms (typ) and FB2 fault
detection is disabled during this period. The soft-start
feature effectively limits the inrush current during startup
(see the Step-Down Regulator Soft-Start Waveforms in
the Typical Operating Characteristics).
Step-Down Regulator Power Good (RESET)
The RESET power-good block is an open-drain-type
design with a capacitor-adjustable, active-low, output
timing. The block monitors the step-down regulator feed-
back node (FB2 in variable mode, or OUTB after divider
in fixed mode) with a 1.0V threshold. The threshold has
a 12mV (typ) hysteresis. RESET goes low when the moni-
tored voltage is below the threshold. When the feedback
node voltage rises above the 1.0V threshold, DEL starts
to charge the capacitor connected there. RESET stays
low until V
DEL
exceeds 1.25V.
Step-Up Regulator
The step-up regulator employs a current-mode, fixed-
frequency PWM architecture to maximize loop bandwidth
and provide fast-transient response to pulsed loads
typical of TFT LCD panel source drivers. The integrated
MOSFET and the built-in digital soft-start function reduce
the number of external components required while con-
trolling inrush currents. The output voltage can be set
from V
IN
to 20V with an external resistive voltage-divider.
(Note: If the HVS function is used, AVDD cannot be set
to this maximum value under normal operating condi-
tions.) The regulator controls the output voltage and the
power delivered to the output by modulating duty cycle
D
SU
of the internal power MOSFET in each switching
cycle. The duty cycle of the MOSFET is approximated by:
AVDD D1 IN
SU
AVDD D1 LX1
V V - V
D
V V - V
+
≈
+