Datasheet

Step-Up, Step-Down Regulator, Gate-On Charge Pump,
and Boost-Buck Regulator for TV TFT LCD Display
MAX17122
______________________________________________________________________________________ 13
Pin Description
PIN NAME FUNCTION
1 GATE
External p-Channel MOSFET Control Output. When the step-up regulator is enabled, GATE
pulls down to control the step-up output during its soft-start. Once GATE is fully on, the step-up
regulator begins switching to regulate the final portion of its soft-start.
2 IN
Input of the Internal 5V Linear Regulator and the Startup Circuitry. Bypass IN to AGND with 0.22FF
close to the IC.
3, 4 IN2
Step-Down Regulator Power Input. Drain of the internal n-channel MOSFET connected between
IN2 and LX2.
5, 24 AGND Analog Ground
6, 7 LX2
Step-Down Regulator Switching Node. LX2 is the source of the internal n-channel MOSFET
connected between IN2 and LX2. Connect the inductor and Schottky catch diode to LX2 and mini-
mize the trace area for low EMI.
8 BST2
Step-Down Regulator Bootstrap Capacitor Connection for High-Side Gate Driver. Connect a 0.1FF
ceramic capacitor from BST2 to LX2.
9 OUTB
Step-Down Regulator Output-Voltage Sense Input. Connect OUTB to the step-down regulator
output.
10 FB2
Step-Down Regulator Feedback Input. Connect FB2 to AGND to select the step-down converter’s
3.3V fixed mode. For adjustable mode, connect FB2 to the center of a resistive voltage-divider
between the step-down regulator output and AGND to set the step-down regulator output voltage.
Place the resistive voltage-divider within 5mm of FB2.
11 GPGD
GON Power-Good Signal Open-Drain Output. GPGD is connected to AGND whenever V
FBP
is less
than the V
FBP
power-good threshold. GPGD is high impedance whenever V
FBP
is greater than the
threshold.
12 DLY1
Step-Up Regulator Delay Input. Connect a capacitor from DLY1 and AGND to set the delay time
between EN2’s rise and the step-up regulator’s soft-start. An 8FA current source charges C
DLY1
.
DLY1 is internally pulled to AGND whenever either EN1 or EN2 is low or VL is below its UVLO
threshold.
13 EN1
Step-Down Enable Input. An 8FA current source charges the capacitor at EN1. When EN1 is high,
the step-down regulator begins operating.
14 EN2
Step-Up and Positive Charge-Pump Linear Regulator Enable Input. Negative linear regulator and
boost-buck regulator enable input. An 8FA current source charges the capacitor at EN2. When
EN2 is high, DLY1 and DLY2 begin charging. DLY1 starts GATE, which turns on the external
p-channel MOSFET and the step-up regulator. DLY2 starts the positive charge-pump linear regula-
tor. EN2 is inactive until after the step-down regulator soft-start is finished.
15 HVS
High-Voltage Stress Mode Control Input. When HVS is high, the RHVS open-drain output connects
to AGND. RHVS is high impedance when HVS is low.
16 FBN
Negative Linear-Regulator Controller Feedback Input. Connect FBN to the center of a resistive
voltage-divider between the negative output and a 3.3V reference to set the negative charge-
pump regulator output voltage. Place the resistive voltage-divider within 5mm of FBN.