Datasheet

where C
OUT
_
CP
is the output capacitor of the charge
pump, I
LOAD
_
CP
is the load current of the charge
pump, and V
RIPPLE_CP
is the peak-to-peak value of the
output ripple.
Output-Voltage Selection
Adjust the positive charge-pump regulator’s output volt-
age by connecting a resistive voltage-divider from the
SRC output to AGND with the center tap connected to
FBP (Figure 1). Select the lower resistor of divider R17
in the 10kΩ to 30kΩ range. Calculate the upper resis-
tor, R16, with the following equation:
where V
FBP
= 1.25V (typ).
Adjust the negative charge-pump regulator’s output
voltage by connecting a resistive voltage-divider from
V
GOFF
to REF with the center tap connected to FBN
(Figure 1). Select R2 in the 20kΩ to 50kΩ range.
Calculate R1 with the following equation:
where V
FBN
= 250mV, V
REF
= 1.25V. Note that REF can
only source up to 50μA, using a resistor less than 20kΩ
for R1 results in higher bias current than REF can supply.
PCB Layout and Grounding
Careful PCB layout is important for proper operation.
Use the following guidelines for good PCB layout:
• Minimize the area of respective high-current loops
by placing each DC-DC converter’s inductor,
diode, and output capacitors near its input capaci-
tors and its LX_ and GND_ pins. For the step-down
regulator, the high-current input loop goes from the
positive terminal of the input capacitor to the IC’s IN
pin, out of LX2, to the inductor, to the positive termi-
nals of the output capacitors, reconnecting the out-
put capacitor and input capacitor ground terminals.
The high-current output loop is from the inductor to
the positive terminals of the output capacitors, to
the negative terminals of the output capacitors, and
to the Schottky diode (D2). For the step-up regula-
tor, the high-current input loop goes from the posi-
tive terminal of the input capacitor to the inductor,
to the IC’s LX1 pin, out of PGND, and to the input
capacitor’s negative terminal. The high-current out-
put loop is from the positive terminal of the input
capacitor to the inductor, to the output diode (D1),
to the positive terminal of the output capacitors,
reconnecting between the output capacitor and
input capacitor ground terminals. Connect these
loop components with short, wide connections.
Avoid using vias in the high-current paths. If vias
are unavoidable, use many vias in parallel to
reduce resistance and inductance.
Create a power ground island for the step-down reg-
ulator, consisting of the input and output capacitor
grounds and the diode ground. Connect all these
together with short, wide traces or a small ground
plane. Similarly, create a power ground island
(PGND) for the step-up regulator, consisting of the
input and output capacitor grounds and the PGND
pin. Create a power ground island (CPGND) for the
positive and negative charge pumps, consisting of
the output (SRC, V
GOFF
) capacitor grounds, and
negative charge-pump diode ground. Connect
CPGND ground plane to PGND together with wide
traces. Maximizing the width of the power ground
traces improves efficiency and reduces output-volt-
age ripple and noise spikes.
• Create an analog ground plane (AGND) consisting
of the AGND pin, all the feedback divider ground
connections, the COMP and DEL capacitor ground
connections, and the device’s exposed backside
pad. Connect PGND and AGND islands by con-
necting the two ground pins directly to the exposed
backside pad. Make no other connections between
the PGND and AGND ground planes.
• Place all feedback voltage-divider resistors as
close as possible to their respective feedback pins.
The divider’s center trace should be kept short.
Placing the resistors far away causes their FB
traces to become antennas that can pick up switch-
ing noise. Care should be taken to avoid running
any feedback trace near LX1, LX2, DRVP, or DRVN.
• Place VIN pin, VL pin, and REF pin bypass capaci-
tors as close as possible to the device. The ground
connection of the VL bypass capacitor should be
connected directly to the AGND pin with a wide
trace.
• Minimize the length and maximize the width of the
traces between the output capacitors and the load
for best transient responses.
• Minimize the size of the LX1 and LX2 nodes while
keeping them wide and short. Keep the LX1 and
LX2 nodes away from feedback nodes (FB1, FB2,
FBP, and FBN) and analog ground. Use DC traces
as a shield, if necessary.
Refer to the MAX17113 evaluation kit for an example of
proper board layout.
RR
VV
VV
FBN GOFF
REF FBN
12=×
-
-
RR
V
V
GON
FBP
17 16 1=×
⎛
⎝
⎜
⎞
⎠
⎟
-
MAX17113
Low-Cost, Multiple-Output
Power Supply for LCD TVs
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