Datasheet

When V
MODE
is less than 0.8 x V
VL
, the switch control
block works in the second mode. The rising edge of
V
CTL
turns on Q1 and turns off Q2, connecting GON to
SRC. An internal n-channel MOSFET, Q3, between
MODE and AGND is also turned on to discharge an
external capacitor between MODE and AGND. The
falling edge of V
CTL
turns off Q3, and an internal 50μA
current source starts charging the MODE capacitor.
Once V
MODE
exceeds V
VL/4
, the switch control block
turns off Q1 and turns on Q2, connecting GON to DRN.
GON can then be discharged through a resisor con-
nected between DRN and PGND or AVDD. Q2 turns off
and stops discharging GON when V
GON
reaches 10
times the voltage on THR.
The switch control block is disabled and DLP is held
low when EN1 or EN2 is low or the IC is in a fault state.
Linear Regulator (VL)
The MAX17113 includes an internal linear regulator. VIN
is the input of the linear regulator. The input voltage
range is between 8V and 16.5V. The output voltage is set
to 5V. The regulator powers the internal MOSFET drivers,
PWM controllers, charge-pump regulators, and logic cir-
cuitry. The total external load capability is 25mA. Bypass
VL to AGND with a minimum 1μF ceramic capacitor.
Reference Voltage (REF)
The reference output is nominally 1.25V, and can
source at least 50μA (see the Typical Operating
Characteristics ). VL is the input of the internal reference
block. Bypass REF with a 0.22μF ceramic capacitor
connected between REF and AGND.
Frequency Selection (FSEL)
The step-down regulator and step-up regulator use the
same internal oscillator. The FSEL input selects the
switching frequency. Table 3 shows the switching fre-
quency based on the FSEL connection. High-frequency
(600kHz) operation optimizes the application for the
smallest component size, trading off efficiency due to
higher switching losses. Low-frequency (450kHz) oper-
ation offers the best overall efficiency at the expense of
component size and board space.
Power-Up Sequence
The step-down regulator starts up when the MAX17113’s
internal reference voltage (REF) is above its undervolt-
age lockout (UVLO) threshold and EN1 is logic-high.
Once the step-down regulator reaches regulation, the
FB2 fault-detection circuit and the negative charge-
pump delay block are enabled. An 8μA current source
at DEL1 charges C
DEL1
linearly. The negative charge-
pump regulator soft-starts when V
DEL1
reaches V
REF
.
FBN fault detection is enabled once the negative
charge-pump soft-start is done. See Figure 6.
The step-up regulator, p-channel MOSFET pass switch,
and positive charge-pump startup sequence begin
when the step-down regulator reaches regulation and
EN2 is logic-high. An 8μA current source at DEL2
charges C
DEL2
linearly and the positive charge pump
is enabled when V
DEL2
reaches V
REF
. When the posi-
tive charge pump is in regulation, an 8μA current
source charges C
DLP
linearly and when V
DLP
reaches
V
REF,
the high-voltage switch is enabled and GON can
be controlled by CTL.
The FB1 fault-detection circuit is enabled after the step-
up regulator reaches regulation, and similarly the FBP
fault-detection circuit is enabled after the positive charge
pump reaches regulation. For nondelayed startups,
capacitors can be omitted from DEL1, DEL2, and DLP.
When their current sources pull the pins above their
thresholds, the associated outputs start.
Power-Down Control
The MAX17113 disables the step-up regulator, positive-
charge-pump regulator input switch control block,
delay block, and high-voltage switch control block
when EN2 is logic-low, or when the fault latch is set.
The step-down regulator and negative charge-pump
regulator are disabled only when EN1 is logic-low or
when the fault latch is set.
Fault Protection
During steady-state operation, if any output of the four
regulators (step-down regulator, step-up regulator,
positive charge-pump regulator, and negative charge-
pump regulator) does not exceed its respective fault-
detection threshold, the MAX17113 activates an inter-
nal fault timer. If any condition or the combination of
conditions indicates a continuous fault for the fault timer
duration (50ms, typ), the MAX17113 triggers a non-
latching output undervoltage fault. After triggering, the
MAX17113 turns off for 160ms (typ) and then restarts
according to the EN1 and EN2 logic states. If, after
restarting, another 50ms fault timeout occurs, the
MAX17113 shuts down for 160ms again, and then
restarts. The restart sequence is repeated 3 times and
after the 50ms fault timeout, the MAX17113 shuts down
and latches off. Once the fault condition is removed,
toggle either EN1 or EN2, or cycle the input voltage to
clear the fault latch and restart the supplies.
MAX17113
Low-Cost, Multiple-Output
Power Supply for LCD TVs
22 ______________________________________________________________________________________
Table 3. Frequency Selection
FSEL SWITCHING FREQUENCY (kHz)
VIN 600
AGND 450