Datasheet

PWM Controller Block
The heart of the PWM control block is a multi-input,
open-loop comparator that sums three signals: the out-
put-voltage signal with respect to the reference voltage,
the current-sense signal, and the slope compensation.
The PWM controller is a direct-summing type, lacking a
traditional error amplifier and the phase shift associated
with it. This direct-summing configuration approaches
ideal cycle-by-cycle control over the output voltage.
When EN1 and EN2 are high, the controller always
operates in fixed-frequency PWM mode. Each pulse
from the oscillator sets the main PWM latch that turns
on the high-side switch until the PWM comparator
changes state.
When EN1 is high and EN2 is low, the controller oper-
ates in skip mode. The skip mode dramatically
improves light-load efficiency by reducing the effective
frequency, which reduces switching losses. It keeps
the peak inductor current at about 0.9A (typ) in an
active cycle, allowing subsequent cycles to be
skipped. Skip mode transitions seamlessly to fixed-
frequency PWM operation as load current increases.
Current Limiting and Lossless Current Sensing
The current-limit circuit turns off the high-side MOSFET
switch whenever the voltage across the high-side
MOSFET exceeds an internal threshold. The actual
current limit is 3A (typ).
For current-mode control, an internal lossless sense
network derives a current-sense signal from the induc-
tor DCR. The time constant of the current-sense net-
work is not required to match the time constant of the
inductor and has been chosen to provide sufficient cur-
rent ramp signal for stable operation at both operating
frequencies. The current-sense signal is AC-coupled
into the PWM comparator, eliminating most DC output-
voltage variation with load current.
Low-Frequency Operation
The step-down regulator of the MAX17113 enters into
low-frequency operating mode if the voltage on OUT is
below 0.8V. In the low-frequency mode, the switching
frequency of the step-down regulator is 1/6 the oscilla-
tor frequency. This feature prevents potentially uncon-
trolled inductor current if OUT is overloaded or shorted
to ground.
Dual-Mode Feedback
The step-down regulator of the MAX17113 supports
both fixed and adjustable output voltages. Connect
FB2 to AGND to enable the 3.3V fixed output voltage.
Connect a resistive voltage-divider between OUT and
AGND with the center tap connected to FB2 to adjust
the output voltage. Choose RB (resistance from FB2 to
AGND) to be between 5kΩ and 50kΩ, and solve for RA
(resistance from OUT1 to FB1) using the equation:
where V
FB2
= 1.25V, and V
OUT
can vary from 1.25V to 5V.
Because of FB2’s (pin 17) close proximity to the noisy
BST (pin 18), a noise filter is required for FB2
adjustable-mode operation. Place a 100pF capacitor
from FB2 to AGND to prevent unstable operation. No fil-
ter is required for 3.3V fixed-mode operation.
Soft-Start
The step-down regulator includes a 7-bit soft-start DAC
that steps its internal reference voltage from 0 to 1.25V in
128 steps. The soft-start period is 3ms (typ) and FB2 fault
detection is disabled during this period. The soft-start fea-
ture effectively limits the inrush current during startup (see
the Step-Down Regulator Soft-Start (Heavy Load) wave-
forms in the Typical Operating Characteristics ).
Step-Up Regulator
The step-up regulator employs a current-mode, fixed-
frequency PWM architecture to maximize loop band-
width and provide fast-transient response to pulsed
loads typical of TFT LCD panel source drivers. The inte-
grated MOSFET and the built-in digital soft-start func-
tion reduce the number of external components
required while controlling inrush currents. The output
voltage can be set from V
IN
to 20V with an external
resistive voltage-divider. The regulator controls the out-
put voltage and the power delivered to the output by
modulating the duty cycle (D) of the internal power
MOSFET in each switching cycle. The duty cycle of the
MOSFET is approximated by:
where V
AVDD
is the output voltage of the step-up regulator.
PWM Controller Block
An error amplifier compares the signal at FB1 to 1.25V
and changes the COMP output. The voltage at COMP
sets the peak inductor current. As the load varies, the
error amplifier sources or sinks current to the COMP
output accordingly to produce the inductor peak cur-
rent necessary to service the load. To maintain stability
at high duty cycles, a slope compensation signal is
summed with the current-sense signal.
D
VV
V
AVDD IN
AVDD
≈
-
RA RB
V
V
OUT
FB
=×
⎛
⎝
⎜
⎞
⎠
⎟
2
1-
MAX17113
Low-Cost, Multiple-Output
Power Supply for LCD TVs
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