Datasheet

MAX17113
Low-Cost, Multiple-Output
Power Supply for LCD TVs
14 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
25 FSEL
Frequency Select Pin. Connect FSEL to AGND for 450kHz operation. Connect to VL or VIN for 600kHz
operation.
26 EN1
Step-Down and Negative Charge-Pump Regulator Enable Input. Input high also enables DLY1 pullup
current.
27 DEL2
Step-Up Regulator and Positive Charge-Pump Delay Input. Connects a capacitor from DEL2 and
AGND to set the delay time between EN2 and the startup of these regulators, or between the step-
down startup and the startup of these regulators if EN1 is high before the step-down starts. An 8μA
current source charges C
DEL2
. DEL2 is internally pulled to AGND through 10 resistance when EN1
or EN2 is low or when VL is below its UVLO threshold.
28 VL
5V Internal Linear Regulator Output. Bypass VL to AGND with 1F minimum. Provides power for the
internal MOSFET driving circuit, the PWM controllers, charge-pump regulators, logic, and reference
and other analog circuitry. Provides 25mA load current when all switching regulators are enabled. VL
is active whenever V
IN
is above its UVLO threshold.
29 EN2
Step-Up and Positive Charge-Pump Regulator Enable Input. Input high also enables DLY2 pullup
current. EN2 is inactive when EN1 is low.
30, 31 PGND Step-Up Regulator Power Ground. Source of the internal power n-channel MOSFET.
32, 33 LX1
Step-Up Regulator Power MOSFET n-Channel Drain and Switching Node. Connects the inductor and
Schottky catch diode to both LX1 pins and minimize the trace area for the lowest EMI.
34 SWI
Step-Up Regulator Internal PMOS Pass Switch Source Input. Connects to the anode of the step-up
regulator Schottky catch diode.
35 SWO Step-Up Regulator Internal pMOS Pass Switch Drain Output
36 FB1
Boost Regulator Feedback Input. Connects FB1 to the center of a resistive voltage-divider between
the boost regulator output and AGND to set the boost regulator output voltage. Place the resistive
voltage-divider within 5mm of FB1.
37 COMP
Compensation Pin for the Step-Up Error Amplifier. Connects a series resistor and capacitor from
COMP to AGND.
38 PGOOD Open-Drain Power-Good Output. Monitors the step-down output voltage.
39 CRST
Power-Good Reset Timing Pin. Connects a capacitor from CRST to AGND to set the step-down
output-rising PGOOD delay.
— EP Exposed Pad = AGND