Datasheet
MAX17113
Low-Cost, Multiple-Output
Power Supply for LCD TVs
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Pin Description
PIN NAME FUNCTION
1 THR
GON Low-Level Regulation Set-Point Input. Connects THR to the center of a resistive voltage-divider
between AVDD and GND to set the V
GON
falling regulation level. The actual level is 10 × V
THR
. See the
High-Voltage Switch Control section for details.
2 DRVP Positive Charge-Pump Driver Output. Connects DRVP to the positive charge-pump flying capacitor(s).
3 GND2 Internal Buck LSS Power Ground
4 SRC Switch Input. Source of the internal high-voltage p-channel MOSFET between SRC and GON.
5 GON
Internal High-Voltage MOSFET Switch Common Terminal. GON is the output of the high-voltage switch-
control block.
6 DRN Switch Input. Drain of the internal high-voltage p-channel MOSFET connected to GON.
7 MODE
High-Voltage Switch-Control Block Mode Selection Input and Timing-Adjustment Input. See the High-
Voltage Switch Control section for details. MODE is high impedance when it is connected to VL. MODE
is internally pulled to GND by a 10Ω resistor for 0.1μs (typ) when the high-voltage switch-control block
is enabled.
8 DLP GON Output Enable. See the High-Voltage Switch Control section for details.
9 FBP
Positive Charge-Pump Regulator Feedback Input. Connects FBP to the center of a resistive voltage-
divider between the positive charge-pump regulator output and AGND to set the positive charge-pump
regulator output voltage. Place the resistive voltage-divider within 5mm of FBP.
10 CPGND Charge Pump and Internal Step-Down Regulator Pulldown Switch Power Ground
11 CTL
High-Voltage Switch-Control Block Timing Control Input. See the High-Voltage Switch Control section
12 DRVN N eg ati ve C har g e- P um p D r i ver Outp ut. C onnects D RV N to the neg ati ve char g e- p um p fl yi ng cap aci tor ( s) .
13, 40 AGND Analog Ground
14 FBN
Negative Charge-Pump Regulator Feedback Input. Connects FBN to the center of a resistive voltage-
divider between the negative output and REF to set the negative charge-pump regulator output voltage.
Place the resistive voltage-divider within 5mm of FBN.
15 REF
Reference Output. Connects a 0.22μF capacitor from REF to AGND. All power outputs are disabled
until REF exceeds its UVLO threshold. REF is active whenever V
IN
is above its UVLO threshold.
16 DEL1
N eg ati ve C har g e- P um p D el ay Inp ut. C onnects a cap aci tor fr om D E L1 and AGN D to set the d el ay ti m e
b etw een the step - d ow n outp ut and the neg ati ve outp ut. An 8μ A cur r ent sour ce char g es C
D E L 1
. D E L1 i s
i nter nal l y p ul l ed to AGN D thr oug h 10Ω r esi stance w hen E N 1 i s l ow or V L i s b el ow i ts U V LO thr eshol d .
17 FB2
Step-Down Regulator Feedback Input. Connects FB2 to GND to select the step-down converter’s 3.3V
fixed mode. For adjustable mode, connect FB2 to the center of a resistive voltage-divider between the
step-down regulator output and GND to set the step-down regulator output voltage. Place the resistive
voltage-divider within 5mm of FB2.
18 BST
Step-Down Regulator Bootstrap Capacitor Connection for High-Side Gate Driver. Connects a 0.1μF
ceramic capacitor from BST to LX2.
19, 20 LX2
Step-Down Regulator Switching Node. LX2 is the source of the internal n-channel MOSFET connected
between IN2 and LX2. Connect the inductor and Schottky catch diode to both LX2 pins to minimize the
trace area for low EMI.
21 OUT Step-Down Regulator Output-Voltage Sense Input. Connects OUT to the step-down regulator output.
22, 23 IN2
Step-Down Regulator Power Input. Drain of the internal n-channel MOSFET connected between IN2 and
LX2.
24 VIN
Input of the Internal 5V Linear Regulator and the Startup Circuitry. Bypass VIN to AGND with 0.22μF
close to the IC.