Datasheet

VGLC and GD
During power-up, the VGLC level-shifter output is high
impedance until V
MAIN
has exceeded 90% of its regula-
tion voltage for more than 64ms, then is driven to VGL
until power-down. During power-down, once either
VDET falls below 1.1V (see the
Voltage Detector section)
or V
IN
falls below 2.0V (typ), VGLC is driven to GHON
and GD is pulled low to turn on an external p-channel
MOSFET connected between GHON and the panel.
Voltage Detector
The voltage detector monitors either V
IN
or V
LDOO
to
generate a logic-low system reset signal (RST) and to
discharge the panel once the voltage being monitored
falls below a desired threshold. The voltage being mon-
itored is sensed through a resistor-divider whose mid-
point is connected to VDET. Once V
VDET
falls below
1.1V, RST is immediately pulled low and the panel is
discharged by driving the level-shifter outputs CKH,
XCKH, and VGLC to V
GHON
, and by pulling GD low to
turn on an external MOSFET connected between
GHON and the panel. At power-up, RST is held low by
the voltage detector such that RST is not released until
a time delay set by C
CD
passes after VDET has
reached 1.15V (1.1V + 50mV hysteresis).
Figure 6 shows the voltage-detector configuration that
is also used in the typical application circuit (Figure 1).
Figure 7 shows the power-up and power-down voltage-
detector timing of the configuration used in Figure 6.
MAX17103/AUO-P1721.14
DC-DC Converter with Integrated Scan Driver,
VGL Controller, Op Amp, and LDO for TFT LCD
______________________________________________________________________________________ 21
CONDITIONS OUTPUTS
V
MAIN
has exceeded
90% of its regulation
voltage for more than
64ms
V
VDET
falls
below 1.1V or
V
IN
falls below
2.0V
VGLC GD
No X High-Z GHON
Yes No VGL GHON
Yes Yes GHON
GHON -
11V (typ)
Table 5. VGLC and GD Logic
X = Don’t care, High-Z = High impedance.
MAX17103
AUO-P1721.14
1.1V
R5
R6
V
LDOO
V
LDOO
DELAY
t
DELAY
= 120k x C
CD
C
CD
VDET
CD
RST
Figure 6. Typical Voltage-Detector Configuration