Datasheet

MAX17103/AUO-P1721.14
DC-DC Converter with Integrated Scan Driver,
VGL Controller, Op Amp, and LDO for TFT LCD
12 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 OPAS
Operational Amplifier Supply Input. Connect to V
MAIN
(Figure 1) and bypass to AGND with a 0.1μF
or greater ceramic capacitor.
2 POS Operational Amplifier Noninverting Input
3 CS
Charge-Sharing Control Input. Charge sharing between the capacitive loads of CKH and XCKH
occurs when CS is low.
4 XCK Level-Shifter Input Signal. The XCK input controls the high-voltage XCKH output while CS is high.
5 CK Level-Shifter Input Signal. The CK input controls the high-voltage CKH output while CS is high.
6 ST Level-Shifter Input Signal. The ST input controls the high-voltage STH output.
7 GHON
Gate-On Supply. GHON is the positive supply voltage for the CKH, XCKH, STH, and VGLC high-
voltage scan driver outputs. Bypass to PGND with a minimum of 0.1μF ceramic capacitor.
8 STH Start Pulse Level-Shifter Output
9 CKH
Level-Shifter Output. Whenever CS is high, CKH toggles between its high state (connected to GHON)
and its low state (connected to VGL) as commanded by the CK input. Whenever CS is low, the CKH
and XCKH drivers are high impedance and the capacitive loads attached to their outputs are
connected together through an internal switch between CK and QS, and an external resistor connected
between the QS and XCKH (R
CS
) to enable charge sharing between the two capacitive loads.
10 QS Charge-Sharing Connection. Connect an external resistor between QS and XCKH.
11 XCKH
Level-Shifter Output. Whenever CS is high, XCKH toggles between its high state (connected to GHON)
and its low state (connected to VGL) as commanded by the XCK input. Whenever CS is low, the CKH
and XCKH drivers are high impedance and the capacitive loads attached to their outputs are
connected together through an internal switch between CK and QS, and an external resistor connected
between the QS and XCKH (R
CS
) to enable charge sharing between the two capacitive loads.
12 VGLC VGL Charge-Sharing Voltage Output
13 VGL
Gate-Off Supply. VGL is the negative supply voltage for the CKH, XCKH, STH, and VGLC high-
voltage driver outputs. Bypass to PGND with a minimum of 1μF ceramic capacitor.
14 N.C. No Connection
15 GD Power-Off Sequence Control Output
16 RST Voltage Detector Open-Drain Output
17 REF
Reference Bypass Terminal. Bypass REF to AGND with a minimum of 0.22μF capacitor close to
the pins.
18 FBN
Gate-Off Linear-Regulator Feedback Input. Connect FBN to the center of a resistive voltage-divider
between the regulator output and REF to set the gate-off linear regulator output voltage.
19 DRVN
Gate-Off Linear-Regulator Base Drive. Open drain of an internal p-channel MOSFET. Connect DRVN
to the base of an external npn pass transistor.
20 CD
Voltage-Detector RST Delay Set. Connect a capacitor to the CD pin to program the RST delay
according to t
DELAY
= 120k x C
CD
(F).