Datasheet

MAX17094
The MAX17094 does not generate an acknowledge
while an internal programming cycle is in progress.
Once the internally timed write cycle has started and
the IVR inputs are disabled, acknowledge polling can
be initiated. This involves sending a START condition
followed by the device address byte. Only if the internal
write cycle has completed does the MAX17094
respond with an acknowledge pulse, allowing the read
or write sequence to continue.
The MAX17094 does not acknowledge a command to
program IVR if V
GON
is not high enough to properly
program the device. Also, a program command must
be preceded by a write command. The IC does not
acknowledge a program command or program IVR
unless the WR data has been modified since the most
recent program command.
Address Byte and Address Pins
The MAX17094’s slave address is determined by the
state of the A0 and A1 address pins. These pins allow up
to four devices to reside on the same I
2
C bus. Address
pins tied to AGND result in a 0 in the corresponding bit
position in the slave address. Conversely, address pins
tied to V
IN
result in a 1 in the corresponding bit positions.
For example, the MAX17094’s slave address byte is 50h
when A0 and A1 pins are grounded (see Figure 8).
Registers
The MAX17094 contains two user-accessible registers:
the data register located at 00h and the access control
register (ACR) located at 02h.
Data Register 00h
The data register contains the WR value that directly
determines the wiper position of the potentiometer, and
the IVR value stored in the nonvolatile memory, which is
used to preset the WR during power-up. The status of
the ACR determines whether WR and/or IVR is
accessed during read and write operations involving
the data register (see the Access Control Register
(ACR) 02h section). When reading and writing to the
data register, the most significant bit (MSB) is ignored.
Figure 9 shows the data register byte.
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
24 ______________________________________________________________________________________
SCL FROM
MASTER
DATA OUTPUT
BY MAX17094
DATA OUTPUT
BY MASTER
CLK1
START
CONDITION
S
1
CLK2
2
CLK8
8
CLK9
9
ACKNOWLEDGE
CLOCK PULSE
ACKNOWLEDGE
NOT ACKNOWLEDGE
D7 D6 D0
Figure 7. I
2
C Bus Acknowledge
0 01 1 0
A1 A2
R/W
SLAVE
ADDRESS*
MSB LSB
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS ADDR0 AND ADDR1.
Figure 8. Address Byte
MSB LSB
X
VCOM DATA BYTE
b6
b5 b4 b3 b2 b1 b0
Figure 9. Data Register Byte