Datasheet

LDO
The power dissipated in the LDO depends on the
LDO’s output current, input voltage, and output voltage:
Scan Driver Outputs
The power dissipated by the scan driver outputs
(Y2–Y8) depends on the scan frequency, the voltage
difference between the power rails across each driver,
and the capacitive load driven by each output.
Assuming the voltage difference between the power
rails of each driver is 30V and all outputs are driving a
load capacitance of 4nF at 50kHz, then the total
expected power dissipation would be:
VCOM Calibrator Interface
The MAX17094 is a slave-only device. The 2-wire I
2
C-
bus-like serial interface (pins SCL and SDA) is
designed to attach to an I
2
C bus that is pulled up to
V
IN
. Connect both SCL and SDA lines to the I
2
C bus
supply through individual pullup resistors. Calculate the
required value of the pullup resistors using:
where t
R
is the rise time in the Electrical Characteristics ,
and C
BUS
is the total capacitance on the bus.
The MAX17094 uses a nonstandard I
2
C interface proto-
col with standard voltage and timing parameters, as
defined in the following subsections.
Bus Not Busy
Both data and clock lines remain high. Data transfers
can be initiated only when the bus is not busy (Figure 6).
Start Data Transfer (S)
Starting from an idle bus state (both SDA and SCL are
high), a high-to-low transition of the SDA line while the
clock (SCL) is high determines a START condition. All
commands must be preceded by a START condition
from a master device on the bus.
Stop Data Transfer (P)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a STOP condition. All opera-
tions must be ended with a STOP condition from the
master device.
Data Valid
The state of the data line represents valid data when, after
a START condition, the data line is stable for the duration
of the high period of the clock signal. The data on the line
must be changed during the low period of the clock sig-
nal. The master generates one clock pulse per bit of data
during write operations and the slave device outputs 1
data bit per clock pulse during read operations. Each
data transfer is initiated with a START condition and termi-
nated with a STOP condition. Two bytes are transferred
between the START and STOP conditions.
Acknowledge/Polling
The MAX17094, when addressed, generates an
acknowledge pulse after the reception of each byte.
The master device must generate an extra clock pulse
that is associated with this acknowledge bit. The device
that acknowledges has to pull down the SDA line dur-
ing the acknowledge clock pulse in such a way that the
SDA line is stable low during the high period of the
acknowledge-related clock pulse. Of course, setup and
hold times must be taken into account. The master sig-
nals an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked
out of the slave. In this case, the slave must leave the
data line high to enable the master to generate the
STOP condition.
R
t
PULLUP
R
≤
C
BUS
PD f C V V
SCAN SCAN PANEL GON GOFF
=× × ×
()
=×
7
750
2
_
-
kkHz nF V W××
()
=430 126
2
.
PD I V V
LDO LOUT LIN LOUT
=×
()
-
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
______________________________________________________________________________________ 23
SCL
SDA
START
CONDITION
S
STOP
CONDITION
P
DATA LINE
STABLE
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 6. I
2
C Bus START, STOP, and Data Change Conditions