Datasheet

MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
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Pin Description
PIN NAME FUNCTION
1 LIN Input of the Internal Linear Regulator. Bypass LIN to GND with a 4μF capacitor close to the IC.
2 LOUT Internal Linear Regulator Output. Bypass LOUT to GND with a 4.7μF capacitor.
3 FBL
Linear Regulator Feedback Pin. Connect external resistor-divider tap here and minimize trace area.
Set V
LOGIC
according to: V
LOGIC
= 0.618V x (1 + R7/R8) (Figure 2).
4, 26, 29 GND Analog Ground
5 ADDR0 Address Select Pin to Set Address for the I
2
C Slave Address
6 ADDR1 Address Select Pin to Set Address for the I
2
C Slave Address
7 SCL I
2
C-Compatible Clock Input
8 SDA I
2
C-Compatible Serial Bidirectional Data Line
9–15 A2–A8 Level-Shifter Logic-Level Inputs
16 SS
Step-Up Regulator Soft-Start Control. Connect a capacitor greater than 200pF between SS and
AGND to set the step-up regulator soft-start timing. SS is connected to AGND when EN is low.
When EN goes high, the capacitor at SS is charged by an internal 5μA current source, slowly
raising the internal current limit. The full LX current limit is available when V
SS
= 1.235V or when
V
MAIN
reaches its regulation threshold, whichever occurs first. If no capacitor is connected, the
soft-start time is controlled by an internal 10ms digital timer.
17 YDCHG Level-Shifter Output Used to Discharge the Panel
18–24 Y2–Y8 Level-Shifter Outputs
25 GOFF
Gate-Off Supply. GOFF is the negative supply voltage for the Y2–Y8 and YDCHG level-shifter
circuitry. Bypass to GND with a minimum 0.1μF ceramic capacitor.
27 GON2
Gate-On Supply. GON2 is the positive supply for the Y7 and Y8 level-shifter circuitry. Bypass to
GND with a minimum 0.1μF ceramic capacitor.
28 GON1
Gate-On Supply. GON1 is the positive supply for the Y2–Y6 and YDCHG level-shifter circuitry.
Bypass to GND with a minimum 0.1μF ceramic capacitor.
30 SET
Full-Scale, Sink-Current Adjustment Input. Connect a resistor, R
SET
, from SET to GND to set the full-
scale adjustable sink current, which is V
AVDD
/(20 x R
SET
). I
OUT
is equal to the current through R
SET
.
31 BGND Operational Amplifier GND
32 VCOM Operational Amplifier Output
33 NEG Operational Amplifier Negative Input
34 POS Operational Amplifier Positive Input
35 OUT
Adjustable Sink-Current Output. OUT connects to the resistive voltage-divider at the op amp input
POS (between AVDD and BGND) that determines the VCOM output voltage. I
OUT
lowers the divider
voltage by a programmable amount.
36 AVDD Op Amp and Internal VL Linear Regulator Supply Input. Bypass AVDD to BGND with a 0.1μF capacitor.
37 FB
Step-Up Regulator Feedback. Connect external resistor-divider tap here and minimize trace area.
Set V
OUT
according to: V
OUT
= 1.235V x (1 + R1/R2) (Figure 2).
38, 39 PGND Power Ground
40, 41 LX Switching Node. Connect inductor/catch diode here and minimize trace area for lowest EMI.
42 FREQ
SMPS Frequency Adjust. Connect a resistor between 30k and 80k to select the step-up
converter’s operating frequency as determined by: f (mHz) = 0.015 x R
FREQ
(k). Leave
unconnected for f = 600kHz.