Datasheet

MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
8 _______________________________________________________________________________________
Timing Diagrams (continued)
V
RESETIN
V
HYST
PROPER WATCHDOG TRIGGER RESETS THE INTERNAL ENABLE COUNTER
t
RESET
= RESET TIMEOUT PERIOD t
OW
= T OPEN WINDOW t
CW
= T CLOSED WINDOW t
WP
= t
CW
+ t
OW
t
WDI
= WDI TRIGGER PERIOD
3 CONSECUTIVE RESETS ENABLE GOES ACTIVE LOW 3 CONSECUTIVE WATCHDOG TRIGGER (WDI) ENABLE GOES ACTIVE HIGH
t
WP
1
2
3
12
3
t
WDI
t
RESET
t
OW
t
CW
t
WP
t
WP
t
WP
t
WDI
t
WDI
t
WDI
V
PON
WDI
ENABLE
RESET
Figure 3. MAX16998B/D Timing Diagram
V
HYST
t
OW
t = 0
t
CW
t
WP
t
RESET
t
CW
≤ t
WDI
≤ t
WP
t
CW
≤ t
WDI
≤ t
WP
t
WP
ENABLE DOES NOT GET ASSERTED IF THE VOLTAGE
AT RESETIN IS BELOW ITS THRESHOLD.
THE WATCHDOG TIMER CLEARS
WHENEVER RESET IS ASSERTED.
t
RRDL
t
WDI
t
WDI
t
WDI
t
WDI
t
WDI
t
WDI
t
WDI
t
WDI
V
RESETIN
V
PON
WDI
1.1V
V
IN
= ENABLE
RESET
t
RESET
t
RESET
Figure 4. RESETIN, RESET , V
IN
, ENABLE , and WDI Voltage Monitoring