Datasheet

MAX16997/MAX16998
WDI falling edge occurs within the watchdog timeout
period (t
WP
) and is considered a late fault that asserts
RESET. In case 3, the WDI falling edge occurs within the
open window period and is considered a good WDI sig-
nal falling edge. In this case, RESET stays high. In case
4, the WDI falling edge occurs within the indeterminate
region. In this case, the RESET state is indeterminate.
These devices assert ENABLE after three consecutive
bad WDI falling edges. ENABLE returns high after three
consecutive good WDI signal falling edges (see Figure 3).
Either a rising edge at RESET or a falling edge at WDI
clears the internal watchdog timer. The watchdog timer
remains cleared while RESET is asserted. The watch-
dog timer begins counting when RESET goes high.
WDI falling edges are ignored when RESET is low.
Applications Information
Selecting the Reset Timeout Capacitor
The reset timeout period is adjustable to accommodate a
variety of µP applications. Adjust the reset timeout period
(t
RESET
) by connecting a capacitor (C
SRT
) between SRT
and ground. See the Reset Timeout Period vs. C
SRT
graph in the Typical Operating Characteristics . Calculate
the reset timeout capacitance using the equation below:
where V
RAMP
is in volts, t
RESET
is in seconds, I
RAMP
is
in nA, and C
SRT
is in nF.
Leakage currents and stray capacitance (e.g., a scope
probe, which induces both) at SRT may cause errors in
the reset timeout period. If precise time control is
required, use capacitors with low leakage current and
high stability.
Selecting the Watchdog
Timeout Capacitor
The watchdog timeout period is adjustable to accom-
modate a variety of µP applications. With this feature,
the watchdog timeout can be optimized for software
execution. The programmer determines how often the
watchdog timer should be serviced. Adjust the watch-
dog timeout period (t
WP
) by connecting a capacitor
(C
SWT
) between SWT and GND. For normal mode
operation, calculate the watchdog timeout capacitance
using the following equation:
where V
RAMP
is in volts, t
WP
is in seconds, I
RAMP
is in nA,
and C
SWT
is in nF. See the Watchdog Timeout Period vs.
C
SWT
graph in the Typical Operating Characteristics .
For the MAX16998B/MAX16998D, the open window size
is factory-set to 50% (MAX16998B) or 75% (MAX16998D)
of the watchdog period. Leakage currents and stray
capacitance (e.g., a scope probe, which induces both) at
SWT may cause errors in the watchdog timeout period. If
precise time control is required, use capacitors with low
leakage current and high stability. To disable the watch-
dog timer function, connect SWT to ground and connect
WDI to either the high- or low-logic state.
Ct
I
V
SWT WP
RAMP
RAMP
=×
×4
Ct
I
V
SRT RESET
RAMP
RAMP
=×
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
12 ______________________________________________________________________________________
t
WDImin
RESET RISING EDGE
t
WDImax
t
WP
(50% or 75%) x t
WP
CASE 1 (FAST FAULT)
CASE 2 (SLOW FAULT)
CASE 3 (GOOD WDI)
CASE 4 (INDETERMINATE)
CLOSED WINDOW OPEN WINDOWINDETERMINATE
Figure 8. The MAX16998B/D Window Watchdog Diagram