Datasheet

MAX16993 Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
www.maximintegrated.com
Maxim Integrated │ 21
Table 3. Output Capacitor Values vs. V
OUT
Table 2. Inductor Values vs. (V
PV_,
V
OUT
)
OUT2/OUT3 Output Capacitor
The minimum capacitor required depends on output volt-
age, maximum device current capability, and the error
amplifier voltage gain. Use the following formula to deter-
mine the required output capacitor value:
REF CS EAMP
OUT(MIN)
CO OUT
V GG
C
2f V
⋅⋅
=
π⋅ ⋅
V
REF
Reference voltage, V
REF
= 1.25V.
G
CS
Internal current sense conductance. See the
Selector Guideforthevalueforeachspecicpart
number.
G
CS
= 1.2S; for 1.5A output channels
G
CS
= 2.4S; for 3.0A output channels
f
CO
Target crossover frequency, 250kHz.
G
EAMP
Errorampliervoltagegainis50V/V
G
EAMP
= 50V/V
where V
REF
is the reference voltage.
Table 3 lists some of the capacitor values for 1.5A
output current and several output voltages. For prop-
er functionality, ceramic capacitors must be used.
Make sure that the self-resonance of the ceramic
capacitors at the converters’ output converter is above
1MHz to avoid instability.
Thermal Considerations
How much power the package can dissipate strongly
depends on the mounting method of the IC to the PCB
and the copper area for cooling. Using the JEDEC test
standard, the maximum power dissipation allowed is
2160mW in the side-wettable QFND package. More
power dissipation can be handled by the package if great
attention is given during PCB layout. For example, using
the top and bottom copper as a heatsink and connect-
ing the thermal vias to one of the middle layers (GND)
transfers the heat from the package into the board more
efficiently, resulting in lower junction temperature at
high power dissipation in some MAX16993 applications.
Furthermore, the solder mask around the IC area on both
top and bottom layers can be removed to radiate the heat
directly into the air. The maximum allowable power dis-
sipation in the IC is as follows:
J ( MAX ) A
MAX
JC CA
(T T )
P
−
=
θ +θ
where T
J(MAX)
is the maximum junction temperature
(+150°C), T
A
istheambientairtemperature,θ
JC
(2.8°C/W
for the side-wettable QFND) is the thermal resistance
from the junction to the case, and θ
CA
is the thermal
resistance from the case to the surrounding air through
thePCB,coppertraces,andthepackagematerials.θ
CA
is directly related to system-level variables and can be
modified to increase the maximum power dissipation. The
QFND package has an exposed thermal pad on its under-
side. This pad provides a low thermal-resistance path for
heat transfer into the PCB. This low thermally resistive
path carries a majority of the heat away from the IC. The
PCB is effectively a heatsink for the IC. The exposed pad
should be connected to a large ground plane for proper
thermal and electrical performance. The minimum size
of the ground plane is dependent upon many system
variables. To create an efficient path, the exposed pad
should be soldered to a thermal landing, which is con-
nected to the ground plane by thermal vias. The thermal
landing should be at least as large as the exposed pad
and can be made larger depending on the amount of free
space from the exposed pad to the other pin landings. A
sample layout is available on the MAX16993 Evaluation
Kit to speed designs.
V
OUT
(V) 3.3 2.5 1.5 0.8
C
OUT
(µF), I
MAX
= 1.5A ≥12 ≥15 ≥25 ≥48
V
PV_
TO V
OUT
(V)
V
PV2/3
= 5.5V,
V
OUT2/3
= 3.3V
V
PV2/3
= 5.5V,
V
OUT2/3
= 2.5V
V
PV2/3
= 5.5V,
V
OUT2/3
= 1.5V
V
PV2/3
= 3.0V,
V
OUT2/3
= 0.8V
INDUCTOR (µH), I
LOAD
= 1.5A 2.2 1.5 1.0 0.56
INDUCTOR (µH), I
LOAD
= 3.0A 1.0 0.68 0.56 0.33