Datasheet

MAX16993 Step-Down Controller with
Dual 2.1MHz Step-Down DC-DC Converters
www.maximintegrated.com
Maxim Integrated │ 18
Gate-charge losses are dissipated by the driver and do
not heat the MOSFET. Therefore, the power dissipation
in the device due to drive losses must be checked. Both
MOSFETs must be selected so that their total gate charge
is low enough; therefore, PV1/ V
OUT1
can power both
drivers without overheating the device:
P
DRIVE
= V
OUT1
x (Q
GTOTH
+ Q
GTOTL
) x f
SW1
where Q
GTOTL
is the low-side MOSFET total gate charge
and Q
GTOTH
is the high-side MOSFET total gate charge.
Select MOSFETs with a Q
G_
total of less than 10nC.
The n-channel MOSFETs must deliver the average
current to the load and the peak current during switching.
Dual MOSFETs in a single package can be an economical
solution. To reduce switching noise for smaller MOSFETs,
use a series resistor in the DH1 path and additional gate
capacitance. Contact the factory for guidance using gate
resistors.
Compensation Network
The device uses a current-mode-control scheme that
regulates the output voltage by forcing the required
current through the external inductor, so the controller
uses the voltage drop across the DC resistance of the
inductor or the alternate series current-sense resistor
to measure the inductor current. Current-mode control
eliminates the double pole in the feedback loop caused
by the inductor and output capacitor, resulting in a smaller
phase shift and requiring less elaborate error-amplifier
compensation than voltage-mode control. A single series
resistor (R
C
) and capacitor (C
C
) is all that is required
to have a stable, high-bandwidth loop in applications
where ceramic capacitors are used for output filtering
(see Figure 4). For other types of capacitors, due to the
higher capacitance and ESR, the frequency of the zero
created by the capacitance and ESR is lower than the
desired closed-loop crossover frequency. To stabilize a
nonceramic output capacitor loop, add another compen-
sation capacitor (C
F
) from COMP1 to GND to cancel this
ESR zero.
The basic regulator loop is modeled as a power modu-
lator, output feedback divider, and an error amplifier
(see Figure 4). The power modulator has a DC gain set by
g
mc
x R
LOAD
, with a pole and zero pair set by R
LOAD
, the
output capacitor (C
OUT
), and its ESR. The loop response
is set by the following equation:
GAIN
MOD(dc)
= g
mc
x R
LOAD
where R
LOAD
= V
OUT
/I
LOUT(MAX)
 in Ω and g
mc
= 1/
(A
V_CS
x R
DC
) in S. A
V_CS
is the voltage gain of the cur-
rent-sense amplifier and is typically 8V/V. R
DC
is the DC
resistanceoftheinductororthecurrent-senseresistorinΩ.
In a current-mode step-down converter, the output capaci-
tor and the load resistance introduce a pole at the follow-
ing frequency:
pMOD
OUT LOAD
1
f
2C R
=
π× ×
The unity-gain frequency of the power stage is set by
C
OUT
and g
mc
:
mc
UGAINpMOD
OUT
g
f
2C
=
π×
The output capacitor and its ESR also introduce a zero at:
zMOD
OUT
1
f
2 ESR C
=
π× ×
When C
OUT
is composed of “n” identical capacitors in
parallel, the resulting C
OUT
= n x C
OUT(EACH)
, and ESR
= ESR
(EACH)
/n. Note that the capacitor zero for a parallel
combination of like-value capacitors is the same as for an
individual capacitor.
The feedback voltage-divider has a gain of GAIN
FB
=
V
FB
/V
OUT
, where V
FB
is 1V (typ).
The transconductance error amplifier has a DC gain of
GAIN
EA(DC)
= g
m,EA
x R
OUT,EA
, where g
m,EA
is the
error amplifier transconductance, which is 660µS (typ),
and R
OUT,EA
is the output resistance of the error ampli-
fier,whichis30MΩ(typ).
Figure 4. Compensation Network
R1
R
ESR
R
C
C
F
C
C
30MΩ
COMP_
C
OUT
R2
CS_
OUT_
FB_
V
REF
CURRENT-MODE
POWER MODULATION
g
mc
= 1/(A
VCS
x R
DC
)
ERROR
AMP
g
MEA
= 660µS