Datasheet

High-Voltage, 2.2MHz, 2A Automotive Step-
Down Converter with Low Operating Current
MAX16974
16 _____________________________________________________________________________________
the voltage drop across the high-side MOSFET. Current-
mode control eliminates the double pole in the feedback
loop caused by the inductor and output capacitor result-
ing in a smaller phase shift and requiring less elaborate
error-amplifier compensation than voltage-mode control.
A simple single-series resistor (R
C
) and capacitor (C
C
)
are all that is required to have a stable, high-bandwidth
loop in applications where ceramic capacitors are
used for output filtering (Figure 5). For other types of
capacitors, due to the higher capacitance and ESR, the
frequency of the zero created by the capacitance and
ESR is lower than the desired closed-loop crossover fre-
quency. To stabilize a nonceramic output capacitor loop,
add another compensation capacitor (C
F
) from COMP to
GND to cancel this ESR zero.
The basic regulator loop is modeled as a power modulator,
output feedback divider, and an error amplifier. The power
modulator has a DC gain set by g
mc
O R
LOAD
, with a pole
and zero pair set by R
LOAD
, the output capacitor (C
OUT
),
and its ESR. The following equations approximate the
value for the gain of the power modulator (GAIN
MOD(DC)
),
neglecting the effect of the ramp stabilization. Ramp stabi-
lization is necessary when the duty cycle is above 50% and
is internally done for the device.
MOD(DC) mc LOAD
GAIN g R= ×
where R
LOAD
= V
OUT
/I
LOUT(MAX)
in I and g
mc
= 3S.
In a current-mode step-down converter, the output
capacitor, its ESR, and the load resistance introduce a
pole at the following frequency:
pMOD
OUT LOAD
1
f
2 C R
=
π × ×
The output capacitor and its ESR also introduce a zero at:
zMOD
OUT
1
f
2 ESR C
=
π × ×
When C
OUT
is composed of “n” identical capacitors in
parallel, the resulting C
OUT
= n O C
OUT(EACH)
and ESR
= ESR
(EACH)
/n. Note that the capacitor zero for a paral-
lel combination of alike capacitors is the same as for an
individual capacitor.
The feedback voltage-divider has a gain of GAIN
FB
=
V
FB
/V
OUT
, where V
FB
is 1V (typ).
The transconductance error amplifier has a DC gain of
GAIN
EA(DC)
= g
m,EA
O R
OUT,EA
, where g
m,EA
is the error
amplifier transconductance, which is 1000FS (typ), and
R
OUT,EA
is the output resistance of the error amplifier 50MI.
A dominant pole (f
dpEA
) is set by the compensation
capacitor (C
C
) and the amplifier output resistance
(R
OUT,EA
). A zero (f
ZEA
) is set by the compensation
resistor (R
C
) and the compensation capacitor (C
C
).
There is an optional pole (f
pEA
) set by C
F
and R
C
to
cancel the output capacitor ESR zero if it occurs near
the crossover frequency (f
C
, where the loop gain equals
1 (0dB)). Thus:
pdEA
C OUT,EA C
1
f
2 C (R R )
=
π × × +
zEA
C C
1
f
2 C R
=
π × ×
pEA
F C
1
f
2 C R
=
π × ×
The loop-gain crossover frequency (f
C
) should be set
below 1/5th of the switching frequency and much higher
than the power-modulator pole (f
pMOD
):
SW
pMOD C
f
f f
5
<< ≤
Figure 5. Compensation Network
R
1
R
2
C
C
C
F
V
REF
V
OUT
R
C
COMP
g
m