Datasheet

MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
23
Maxim Integrated
Applications Information
PCB Layout Guidelines
Make the controller ground connections as follows: cre-
ate a small analog ground plane near the IC by using
any of the PCB layers. Connect this plane to SGND and
use this plane for the ground connection for the SUP
bypass capacitor, compensation components, feed-
back dividers, and FOSC resistor.
Place all power components on the top side of the
board and run the power stage currents, especially
large high-frequency components, using traces or cop-
per fills on the top side only, without adding vias.
On the top side, lay out a large PGND copper area for
the output, and connect the bottom terminals of the high-
frequency input capacitors, output capacitors, and the
source terminals of the low-side MOSFET to that area.
Keep the power traces and load connections short,
especially at the ground terminals. This practice is
essential for high efficiency and jitter-free operation. Use
thick copper PCBs (2oz. vs. 1oz.) to enhance efficiency.
Place the controller IC adjacent to the synchronous
rectifier MOSFET (NL) and keep the connections for LX,
PGND, DH, and DL short and wide. Use multiple small
vias to route these signals from the top to the bottom
side if these signals need to be routed in the bottom
layer. The gate current traces must be short and wide,
measuring 50 mils to 100 mils wide if the low-side
MOSFET is 1in from the controller IC. Connect the
PGND trace from the IC close to the source terminal of
the low-side MOSFET.
Route high-speed switching nodes (BST, LX, DH, and
DL) away from the sensitive analog areas (FOSC,
COMP, and FB). Group all SGND-referred and feed-
back components close to the IC. Keep the FB and
compensation network nets as small as possible to pre-
vent noise pickup.
Place the sense resistor close to the IC with short,
direct traces, making a Kelvin-sense connection to the
current-sense resistor.
Place BIAS capacitor close to the IC and minimize vias in
the path in order to minimize transients on the BIAS line.
Figure 6. Typical Operating Circuit for V
OUT
= 5V
MAX16955
R4
R2
D2
RED
D1
BIAS FB
OUT
C2
FOSC
FSYNC
SGND
R5
R1
R3
COMP
C9
C8
C7
C1 C3
C4
SUP
BST
N1-A
N1-B
PGND
DL
L1
LX
V
OUT
5V
6
4
3
PGOOD
10
5
V
L_IN
EN
2
V
EN
1
V
BAT
5.5V TO 28V
713
C6 C5
9
11
12
14
CS
8
16
DH
15