Datasheet

MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
22
Maxim Integrated
During recharge, the internal bootstrap switch acts as a
resistor, resulting in an RC circuit with the associated
time constants. Two τs (time constants) are necessary
to charge from 90% to 99%. The maximum allowable
capacitance is, therefore:
When in dropout, t
OFF(MIN)
is the minimum on-time of
the low-side switch and is approximately half the clock
period. When not in dropout, t
OFF(MIN)
= 1 - D
MAX
.
Should this value be lower than the ideal capacitance
and assuming that the minimum bootstrap capacitor
should be large enough to supply 2V (typ) effective
gate voltage:
Should the minimum value still be too large to be
recharged sufficiently, a parallel bootstrap Schottky
diode may be necessary.
Power Dissipation
The MAX16955’s maximum power dissipation depends
on the thermal resistance from the die to the ambient
environment and the ambient temperature. The thermal
resistance depends on the device package, PCB cop-
per area, other thermal mass, and airflow.
The device’s power dissipation depends on the internal
linear regulator current consumption (P
LIN
) and the
dynamic gate current (P
GATE
):
P
T
= P
LIN
+ P
GATE
Linear power is the average bias current times the volt-
age drop from V
SUP
to V
BIAS
:
P
LIN
= I
BIAS,AV
× (V
SUP
- V
BIAS
)
where I
BIAS,AV
= I
SUP(MAX)
+ f
SW
× (Q
G_DH(MAX)
+
Q
G_DL(MAX)
), I
SUP(MAX)
is 2mA, f
SW
is the switching
frequency programmed at FOSC, and Q
G_
is the MOS-
FET data sheet’s total gate-charge specification limits
at V
GS
= 5V.
Dynamic power is the average power during charging
and discharging of both the external gates per period
of oscillation:
where:
is the frequency-dependent power, dissipated during
one turn-on and turn-off cycle of each of the external
n-channel MOSFETs. R
HS/LS
is the on-resistance of the
NH and NL.
To estimate the temperature rise of the die, use the fol-
lowing equation:
T
J
= T
A
+ (P
T
×θ
JA
)
where θ
JA
is the junction-to-ambient thermal resistance
of the package, P
T
is power dissipated in the device,
and T
A
is the ambient temperature. The θ
JA
is 38.3°C/W
for the 16-pin TSSOP package on multilayer boards,
with the conditions specified by the respective JEDEC
standards (JESD51-5, JESD51-7). If actual operating
conditions significantly deviate from those described in
the JEDEC standards, then an accurate estimation of
the junction temperature requires a direct measurement
of the case temperature (T
C
). Then, the junction temper-
ature can be calculated using the following equation:
T
J
= T
C
+ (P
T
×θ
JC
)
Use 3°C/W as θ
JC
thermal resistance for the 16-pin
TSSOP package. The case-to-ambient thermal resis-
tance (θ
CA
) is dependent on how well the heat is trans-
ferred from the PCB to the ambient. Therefore, solder
the exposed pad of the TSSOP package to a large
copper area to spread heat through the board surface,
minimizing the case-to-ambient thermal resistance. Use
large copper areas to keep the PCB temperature low.
20210
2
6
××≈×
−
V
R
t
W
Hz
BIAS
HS LS
GRISE
/
,
.
P
V
R
tf
GATE
BIAS
HS LS
GRISE SW
=× × ×2
2
/
,
C
Q
VVV
BST MIN
G
BIAS MIN TH TYP
()
() ()
=
−−2
C
t
R
BST MAX
OFF MIN
BST MAX
()
()
()
=
×2