Datasheet

MAX16932/MAX16933
2.2MHz, 36V, Dual Buck
with 20µA Quiescent Current
18Maxim Integrated
In standby mode, the inductor current becomes discon-
tinuous, with peak currents set by the idle-mode current-
sense threshold (V
CS,SKIP
= 26mV (typ)).
Transient Considerations
The output capacitor must be large enough to absorb
the inductor energy while transitioning from no-load to
full-load condition without tripping the overvoltage fault
protection. The total output voltage sag is the sum of
the voltage sag while the inductor is ramping up and the
voltage sag before the next pulse can occur. Therefore:
( )
( )
∆
=
−
∆ −∆
+
2
LOAD(MAX)
OUT
SAG IN MAX OUT
LOAD(MAX)
SAG
LI
C
2V (V xD V )
I tt
V
where D
MAX
is the maximum duty factor (approximately
95%), L is the inductor value in µH, C
OUT
is the output
capacitor value in µF, t is the switching period (1/f
SW
) in
µs, and Dt equals (V
OUT
/V
IN
) x t.
The MAX16932/MAX16933 use a peak current-mode
control scheme that regulates the output voltage by forc-
ing the required current through the external inductor, so
the controller uses the voltage drop across the DC resis-
tance of the inductor or the alternate series current-sense
resistor to measure the inductor current. Current-mode
control eliminates the double pole in the feedback loop
caused by the inductor and output capacitor resulting in
a smaller phase shift and requiring less elaborate error-
amplifier compensation than voltage-mode control. A
single series resistor (R
C
) and capacitor (C
C
) is all that is
required to have a stable, high-bandwidth loop in appli-
cations where ceramic capacitors are used for output
filtering (see Figure 2). For other types of capacitors, due
to the higher capacitance and ESR, the frequency of the
zero created by the capacitance and ESR is lower than
the desired closed-loop crossover frequency. To stabi-
lize a non-ceramic output capacitor loop, add another
compensation capacitor (C
F
) from COMP to AGND to
cancel this ESR zero.
The basic regulator loop is modeled as a power modula-
tor, output feedback divider, and an error amplifier as
shown in Figure 2. The power modulator has a DC gain
set by g
mc
x R
LOAD
, with a pole and zero pair set by
R
LOAD
, the output capacitor (C
OUT
), and its ESR. The
loop response is set by the following equations:
MOD(dc) mc LOAD
GAIN g R= ×
where R
LOAD
= V
OUT
/I
LOUT(MAX)
in I and g
mc
=1/(A
V_CS
x R
DC
) in S. A
V_CS
is the voltage gain of the current-sense
amplifier and is typically 11V/V. R
DC
is the DC resistance
of the inductor or the current-sense resistor in I.
In a current-mode step-down converter, the output
capacitor and the load resistance introduce a pole at the
following frequency:
pMOD
OUT LOAD
1
f
2C R
=
π× ×
The unity gain frequency of the power stage is set by
C
OUT
and g
mc
:
mc
UGAINpMOD
OUT
g
f
2C
=
π×
The output capacitor and its ESR also introduce a zero at:
zMOD
OUT
1
f
2 ESR C
=
π× ×
When C
OUT
is composed of “n” identical capacitors in
parallel, the resulting C
OUT
= nxC
OUT(EACH)
, and ESR =
ESR
(EACH)
/n. Note that the capacitor zero for a parallel
combination of alike capacitors is the same as for an
individual capacitor.
Figure 2. Compensation Network
CS_
OUT_
FB_
R1
R
ESR
C
C
C
F
R
C
R2
V
REF
C
OUT
g
mc
= 1/(A
VCS
x R
DC
)
CURRENT MODE
POWER
MODULATION
ERROR
AMP
COMP_
g
mea
= 1200µS
30MI