Datasheet

MAX16932/MAX16933
2.2MHz, 36V, Dual Buck
with 20µA Quiescent Current
12Maxim Integrated
Buck Controllers
The MAX16932/MAX16933 provide two buck controllers
with synchronous rectification. The step-down control-
lers use a PWM, current-mode control scheme. External
logic-level MOSFETs allow for optimized load-current
design. Fixed-frequency operation with optimal interleav-
ing minimizes input ripple current from the minimum to
the maximum input voltages. Output-current sensing
provides an accurate current limit with a sense resistor or
power dissipation can be reduced using lossless current
sensing across the inductor.
Soft-Start
Once a buck converter is enabled by driving the cor-
responding EN_ high, the soft-start circuitry gradually
ramps up the reference voltage during soft-start time
(t
SSTART
= 6ms (typ)) to reduce the input surge currents
during startup. Before the device can begin the soft-start,
the following conditions must be met:
1) V
BIAS
exceeds the 3.4V (max) undervoltage lockout
threshold.
2) V
EN_
is logic-high.
Switching Frequency/External
Synchronization
The MAX16932 provides an internal oscillator adjust-
able from 1MHz to 2.2MHz. The MAX16933 provides
an internal oscillator adjustable from 200kHz to 1MHz.
High-frequency operation optimizes the application for
the smallest component size, trading off efficiency to
higher switching losses. Low-frequency operation offers
the best overall efficiency at the expense of component
size and board space. To set the switching frequency,
connect a resistor R
FOSC
from FOSC to AGND. See
TOC8 and TOC9 (Switching Frequency vs. R
FOSC
) in
the Typical Operating Characteristics to determine the
relationship between switching frequency and R
FOSC
.
Buck 1 is synchronized with the internal clock-signal
rising edge, while buck 2 is synchronized with the clock-
signal falling edge.
The devices can be synchronized to an external clock by
connecting the external clock signal to FSYNC. A rising
edge on FSYNC resets the internal clock. Keep the FSYNC
frequency between 110% and 150% of the internal fre-
quency. The FSYNC signal should have a 50% duty cycle.
Light-Load Efficiency Skip Mode
(V
FSYNC
= 0V)
Drive FSYNC low to enable skip mode. In skip mode, the
devices stop switching until the FB voltage drops below
the reference voltage. Once the FB voltage has dropped
below the reference voltage, the devices begin switching
until the inductor current reaches 20% (skip threshold)
of the maximum current defined by the inductor DCR or
output shunt resistor.
Forced-PWM Mode (V
FSYNC
= High)
Driving FSYNC high prevents the devices from enter-
ing skip mode by disabling the zero-crossing detection
of the inductor current. This forces the low-side gate-
driver waveform to constantly be the complement of
the high-side gate-drive waveform, so the inductor cur-
rent reverses at light loads and discharges the output
capacitor. The benefit of forced PWM mode is to keep the
switching frequency constant under all load conditions.
However, forced-frequency operation diverts a consider-
able amount of the output current to PGND, reducing the
efficiency under light-load conditions.
Forced-PWM mode is useful for improving load-transient
response and eliminating unknown frequency harmonics
that may interfere with AM radio bands.
Spread Spectrum
The MAX16932ATIS, MAX16932ATIU, and
MAX16933ATIS feature enhanced EMI performance.
They perform Q6% dithering of the switching frequency
to reduce peak emission noise at the clock frequency
and its harmonics, making it easier to meet stringent
emission limits.
When using an external clock source (i.e., driving the
FSYNC input with an external clock), spread spectrum
is disabled.
Buck 2 Switching Frequency
For the MAX16932ATIT and MAX16932ATIU, the switch-
ing frequency of buck 2 is set to 1/2 of f
SW
(buck 1
switching frequency). When using these devices, the
external components of buck 2 should be sized to
account for the reduced switching frequency (see the
Design Procedure section).